Catch up with Pavel moving things to core/lib. I suspect more will follow.

1 files changed, 4 insertions, 7 deletions

diff --git a/config/core.cfg b/config/core.cfg
index 222a8e0..94cba14 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -86,10 +86,6 @@ cores = sha256 aes trng modexp
 # Make me one with everything, except we want two modexp cores for parallel CRT
 cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384
 
-[project hsm-super]
-# super-size it
-cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes aes aes modexp modexp modexp ecdsa256 ecdsa256 ecdsa256 ecdsa384 ecdsa384 ecdsa384
-
 # [core] sections
 #
 # vfiles: A list of Verilog files to include in the vfiles list when
@@ -213,7 +209,8 @@ vfiles =
 	math/modexpa7/src/rtl/pe/modexpa7_adder32.v
 	math/modexpa7/src/rtl/pe/modexpa7_subtractor32.v
 	math/modexpa7/src/rtl/pe/modexpa7_systolic_pe.v
-	math/modexpa7/src/rtl/util/bram_1rw_readfirst.v
+	lib/memory/bram_1rw_readfirst.v
+	lib/memory/bram_1rw_1ro_readfirst.v
 
 [core modexps6]
 # ModExp for Xilinx Spartan-6
@@ -321,7 +318,7 @@ vfiles =
 	math/ecdsalib/rtl/modular/modular_subtractor.v
 	math/ecdsalib/rtl/multiword/mw_comparator.v
 	math/ecdsalib/rtl/multiword/mw_mover.v
-	math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v
+	lib/memory/bram_1rw_1ro_readfirst.v
 
 [core ecdsa384]
 # ECDSA-P384 point multipler
@@ -373,4 +370,4 @@ vfiles =
 	math/ecdsalib/rtl/modular/modular_subtractor.v
 	math/ecdsalib/rtl/multiword/mw_comparator.v
 	math/ecdsalib/rtl/multiword/mw_mover.v
-	math/ecdsalib/rtl/util/bram_1rw_1ro_readfirst.v
+	lib/memory/bram_1rw_1ro_readfirst.v