//======================================================================
//
// global_selector.v
// -----------------
// Top level wrapper that creates the Cryptech coretest system.
// The wrapper contains instances of external interface, coretest
// and the core to be tested. And if more than one core is
// present the wrapper also includes address and data muxes.
//
//
// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module global_selector
(
input wire sys_clk,
input wire sys_rst,
input wire sys_ena,
input wire [13: 0] sys_eim_addr,
input wire sys_eim_wr,
input wire sys_eim_rd,
output wire [31 : 0] sys_read_data,
input wire [31 : 0] sys_write_data
);
//----------------------------------------------------------------
// Address Decoder
//----------------------------------------------------------------
wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
//----------------------------------------------------------------
// Core Address Table
//----------------------------------------------------------------
localparam CORE_ADDR_BOARD_REGS = 6'd0;
localparam CORE_ADDR_COMM_REGS = 6'd1;
//----------------------------------------------------------------
// Board-Level Registers
//----------------------------------------------------------------
wire [31: 0] read_data_board;
wire enable_board = sys_ena && (addr_core_num == CORE_ADDR_BOARD_REGS);
board_regs board_regs
(
.clk(sys_clk),
.rst(sys_rst),
.cs(enable_board & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(addr_core_reg),
.write_data(sys_write_data),
.read_data(read_data_board)
);
//----------------------------------------------------------------
// Communication-Channel Registers
//----------------------------------------------------------------
wire [31: 0] read_data_comm;
wire enable_comm = sys_ena && (addr_core_num == CORE_ADDR_COMM_REGS);
comm_regs comm_regs
(
.clk(sys_clk),
.rst(sys_rst),
.cs(enable_comm & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(addr_core_reg),
.write_data(sys_write_data),
.read_data(read_data_comm)
);
//----------------------------------------------------------------
// SHA-1
//----------------------------------------------------------------
`ifdef USE_CORE_SHA1
wire [31: 0] read_data_sha1;
wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
sha1 sha1_inst
(
.clk(sys_clk),
.reset_n(~sys_rst),
.cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(addr_core_reg),
.write_data(sys_write_data),
.read_data(read_data_sha1)
);
`endif
//----------------------------------------------------------------
// SHA-256
//----------------------------------------------------------------
`ifdef USE_CORE_SHA256
wire [31: 0] read_data_sha256;
wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
sha256 sha256_inst
(
.clk(sys_clk),
.reset_n(~sys_rst),
.cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(addr_core_reg),
.write_data(sys_write_data),
.read_data(read_data_sha256)
);
`endif
//----------------------------------------------------------------
// SHA-512
//----------------------------------------------------------------
`ifdef USE_CORE_SHA512
wire [31: 0] read_data_sha512;
wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
sha512 sha512_inst
(
.clk(sys_clk),
.reset_n(~sys_rst),
.cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
.address(addr_core_reg),
.write_data(sys_write_data),
.read_data(read_data_sha512)
);
`endif
//----------------------------------------------------------------
// Output (Read Data) Multiplexor
//----------------------------------------------------------------
reg [31: 0] sys_read_data_mux;
assign sys_read_data = sys_read_data_mux;
always @*
//
case (addr_core_num)
//
CORE_ADDR_BOARD_REGS:
sys_read_data_mux = read_data_board;
CORE_ADDR_COMM_REGS:
sys_read_data_mux = read_data_comm;
//
default:
sys_read_data_mux = {32{1'b0}};
//
endcase
endmodule
//======================================================================
// EOF global_selector.v
//======================================================================
