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Diffstat (limited to 'rtl/clkmgr_mmcm_ctrl.v')
| -rw-r--r-- | rtl/clkmgr_mmcm_ctrl.v | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/rtl/clkmgr_mmcm_ctrl.v b/rtl/clkmgr_mmcm_ctrl.v new file mode 100644 index 0000000..6d22291 --- /dev/null +++ b/rtl/clkmgr_mmcm_ctrl.v @@ -0,0 +1,117 @@ +//====================================================================== +// +// clkmgr_mmcm_ctrl.v +// ------------------ +// PLL reset generator and lock monitor. +// +// +// Author: Pavel Shatov +// Copyright (c) 2019, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module clkmgr_mmcm_ctrl +( + input clk_in, + input reset_n_in, + input locked_in, + output reset_out +); + + // + // Timer Settings + // + localparam [13:0] tmr_zero = {14{1'b0}}; + localparam [13:0] tmr_last = {14{1'b1}}; + reg [13:0] tmr = tmr_zero; + wire [13:0] tmr_next = tmr + 1'b1; + wire [ 9:0] tmr_msb = tmr[13:4]; + + wire tmr_about_to_wrap = tmr == tmr_last; + wire tmr_msb_is_zero = tmr_msb == 10'd0; + + // + // Lock Counting and Monitoring + // + reg [1:0] pll_seen_locks = 2'd0; + wire [1:0] pll_seen_locks_next = (pll_seen_locks < 2'd3) ? pll_seen_locks + 1'b1 : pll_seen_locks; + + (* SHREG_EXTRACT="NO" *) + (* EQUIVALENT_REGISTER_REMOVAL="NO" *) + reg [3:0] pll_stable_lock_shreg = 4'h0; + wire pll_stable_lock = pll_stable_lock_shreg[3]; + + wire pll_needs_reset = (pll_seen_locks != 2'd1) || !pll_stable_lock; + + // + // Output Register + // + reg reset_out_r = 1'b1; + assign reset_out = reset_out_r; + + // + // Timer Increment/Wrap Logic + // + always @(posedge clk_in or negedge reset_n_in) + // + if (!reset_n_in) tmr <= tmr_zero; + else begin + if (!tmr_about_to_wrap) tmr <= tmr_next; + else if (pll_needs_reset) tmr <= tmr_zero; + end + + // + // Lock Counter + // + always @(posedge locked_in or posedge reset_out) + // + if (reset_out) pll_seen_locks <= 2'd0; + else pll_seen_locks <= pll_seen_locks_next; + + // + // Lock Monitor + // + always @(posedge clk_in or negedge locked_in) + // + if (!locked_in) pll_stable_lock_shreg <= 4'h0; + else pll_stable_lock_shreg <= {pll_stable_lock_shreg[2:0], 1'b1}; + + // + // Reset Generator + // + always @(posedge clk_in or negedge reset_n_in) + // + if (!reset_n_in) reset_out_r <= 1'b1; + else reset_out_r <= tmr_msb_is_zero; + +endmodule + +//====================================================================== +// EOF clkmgr_mmcm_ctrl.v +//====================================================================== |