diff options
Diffstat (limited to 'rtl/alpha_clkmgr.v')
| -rw-r--r-- | rtl/alpha_clkmgr.v | 182 |
1 files changed, 91 insertions, 91 deletions
diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v index 5c4099e..0f5f912 100644 --- a/rtl/alpha_clkmgr.v +++ b/rtl/alpha_clkmgr.v @@ -7,7 +7,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved. +// Copyright (c) 2016, 2018-2019 NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -38,101 +38,101 @@ //====================================================================== module alpha_clkmgr - ( - input wire fmc_clk, // signal from clock pin - - output wire sys_clk, // buffered system clock output
- output wire sys_rst_n // system reset output (async set, sync clear, active-low) - ); - - - // - // Settings - //
-
- /*
- * fmc_clk is 90 MHz, sys_clk is also 90 MHz routed through an MMCM.
- *
- * VCO frequency is 1080 MHz.
- *
- */ - localparam CLK_OUT_MUL = 12.0; - localparam CLK_OUT_DIV = 12.0;
- localparam CLK_OUT_PHI = 45.0;
+(
+ input wire fmc_clk, // signal from clock pin
+ output wire io_clk, // buffered i/o clock
+ output wire sys_clk, // buffered system clock output
+ output wire sys_rst_n, // system reset output (async set, sync clear, active-low)
+ output wire core_clk // buffered high speed core clock +); - // - // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive. - // - - wire gclk_int; // buffered input clock - wire mmcm_reset; // reset input - wire mmcm_locked; // output clock valid - wire gclk_missing; // input clock stopped
- - clkmgr_mmcm # - ( - .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64 - .CLK_OUT_DIV (CLK_OUT_DIV), // 1..128
- .CLK_OUT_PHI (CLK_OUT_PHI) // 0.0..360.0
- ) - mmcm - ( - .gclk_in (fmc_clk), - .reset_in (mmcm_reset), - - .gclk_out (gclk_int), - .gclk_missing_out (gclk_missing), - - .clk_out (sys_clk),
- .clk_valid_out (mmcm_locked) - );
- - - - // - // MMCM Reset Logic - // - - /* MMCM should be reset on power-up and when the input clock is stopped.
- * Note that MMCM requires active-high reset, so the shift register is
- * preloaded with 1's and then gradually filled with 0's. - */ - - reg [15: 0] mmcm_rst_shreg = {16{1'b1}}; // 16-bit shift register - - always @(posedge gclk_int or posedge gclk_missing) - // - if (gclk_missing == 1'b1) - mmcm_rst_shreg <= {16{1'b1}}; - else - mmcm_rst_shreg <= {mmcm_rst_shreg[14:0], 1'b0}; - - assign mmcm_reset = mmcm_rst_shreg[15]; - - - // - // System Reset Logic - // - - /* System reset is asserted for 16 cycles whenever MMCM aquires lock. Note - * that system reset is active-low, so the shift register is preloaded with - * 0's and gradually filled with 1's. - */ - - reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register - - always @(posedge sys_clk or posedge gclk_missing or negedge mmcm_locked) - // - if ((gclk_missing == 1'b1) || (mmcm_locked == 1'b0)) - sys_rst_shreg <= {16{1'b0}}; - else if (mmcm_locked == 1'b1) - sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1}; - - assign sys_rst_n = sys_rst_shreg[15]; +
+ //
+ // Parameters
+ //
+ parameter integer CLK_CORE_MULT = 4;
+ +
+ //
+ // STARTUPE2
+ //
+ wire cfg_mclk; // 65 MHz (+/- 50%) internal oscillator
+ wire cfg_eos; // end-of-startup flag
+
+ STARTUPE2 #
+ ( + .SIM_CCLK_FREQ (0.0), // config clock frequency for simulation + .PROG_USR ("FALSE") // only used with encrypted bitstreams + ) + STARTUPE2_inst
+ ( + .CLK (1'b0), // no external clock + .CFGCLK (), // config clock (unused) + .CFGMCLK (cfg_mclk), // config clock
+ .EOS (cfg_eos), // end-of-startup flag +
+ .USRCCLKO (1'b0), // custom clock for configuration memory access (unused) + .USRCCLKTS (1'b0), // UG470 recommends this to be held low + .USRDONEO (1'b1), // custom value to drive onto DONE pin (unused) + .USRDONETS (1'b1), // tri-state DONE pin (unused) +
+ .GSR (1'b0), // UG470 recommends hardwiring this low + .GTS (1'b0), // UG470 recommends this to be tied low + + .PREQ (), // unused when PROG_USR is disabled + .PACK (1'b0), // only used when PROG_USR is enabled
+
+ .KEYCLEARB (1'b1) // unused
+ ); +
+
+ // + // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive. + // + wire mmcm_reset; // reset input + wire mmcm_locked; // output clock valid + + clkmgr_mmcm #
+ (
+ .CLK_CORE_MULT(CLK_CORE_MULT)
+ )
+ mmcm_inst + ( + .fmc_clk_in (fmc_clk),
+ .rst_in (mmcm_reset), + + .io_clk_out (io_clk),
+ .sys_clk_out (sys_clk),
+ .core_clk_out (core_clk),
+ .locked_out (mmcm_locked) + );
+
+ //
+ // MMCM Controller
+ //
+ clkmgr_mmcm_ctrl mmcm_ctrl_inst + (
+ .clk_in (cfg_mclk), + .reset_n_in (cfg_eos), + .locked_in (mmcm_locked), + .reset_out (mmcm_reset) + );
+
+ + // + // System Reset Logic + //
+ clkmgr_reset_gen #(.SHREG_WIDTH(16)) reset_gen_inst
+ (
+ .clk_in (sys_clk),
+ .locked_in (mmcm_locked),
+ .reset_n_out (sys_rst_n)
+ ); endmodule +
//====================================================================== // EOF alpha_clkmgr.v |