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-rw-r--r--build/Makefile8
1 files changed, 7 insertions, 1 deletions
diff --git a/build/Makefile b/build/Makefile
index ca5d735..218e444 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -20,7 +20,10 @@ ucf ?= ../ucf/$(project).ucf
# Verilog include directories, if needed
-vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+vlgincdir = \
+ $(CORE_TREE)/lib/lowlevel \
+ $(CORE_TREE)/math/ecdsalib/rtl/microcode \
+ $(CORE_TREE)/lib/util
all: $(project).bit
@@ -47,7 +50,10 @@ vfiles = \
$(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \
$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
+ $(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm_ctrl.v \
./core_selector.v \
+ $(CORE_TREE)/platform/alpha/rtl/clkmgr_reset_gen.v \
+ $(CORE_TREE)/platform/common/extra/reset_replicator.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \