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Diffstat (limited to 'build/Makefile')
-rw-r--r-- | build/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile index ea8d032..aed01df 100644 --- a/build/Makefile +++ b/build/Makefile @@ -44,6 +44,10 @@ rsa: $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa $(MAKE) project=$(project)_rsa ucf=$(ucf) +mkmif: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s mkmif + $(MAKE) project=$(project)_mkmif ucf=$(ucf) + # Verilog files that always go with builds on this platform. vfiles = \ |