1 files changed, 177 insertions, 0 deletions
diff --git a/build/Makefile.vivado b/build/Makefile.vivado
new file mode 100644
index 0000000..557eca2
--- /dev/null
+++ b/build/Makefile.vivado
@@ -0,0 +1,177 @@
+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE	:= $(abspath ../../..)
+
+# Parameters
+
+project		?= alpha_fmc
+top_module	= alpha_fmc_top
+board		= alpha
+part		= xc7a200tfbg484-1
+
+# Project configuration
+
+CONFIG          = $(CORE_TREE)/platform/common/config
+CONFIG_PROJECT	= hsm
+CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(board)
+
+
+# Intermediate TCL stuff
+
+tcl_warning_message	= generated automatically, don't edit
+
+tcl_create_project		= create_project.tcl
+tcl_run_synthesis		= run_synthesis.tcl
+tcl_run_implementation	= run_implementation.tcl
+tcl_generate_bitstream	= generate_bitstream.tcl
+
+# Project settings
+
+proj_sources_set		= sources_1
+proj_constraints_set	= constrs_1
+proj_synthesis_run		= synth_1
+proj_implementation_run	= impl_1
+
+# Extra command line options
+
+vivado_options = -nojournal -nolog
+
+# Helper variables
+
+synth_run					= $(project).runs/$(proj_synthesis_run)
+impl_run					= $(project).runs/$(proj_implementation_run)
+
+# Implementation constraints
+
+xdcfiles = \
+	$(CORE_TREE)/platform/$(board)/xdc/$(project)_clocks.xdc \
+	$(CORE_TREE)/platform/$(board)/xdc/$(project)_pinout.xdc \
+	$(CORE_TREE)/platform/$(board)/xdc/$(project)_timing.xdc
+
+# Verilog include directories, if needed
+
+vlogincdirs = \
+	$(CORE_TREE)/lib/lowlevel \
+	$(CORE_TREE)/math/ecdsalib/rtl/microcode \
+	$(CORE_TREE)/lib/util
+
+# Verilog files that always go with builds on this platform.
+
+vfiles = \
+	$(CORE_TREE)/platform/alpha/rtl/alpha_fmc_top.v \
+	$(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \
+	$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
+	$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
+	$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm_ctrl.v \
+	./core_selector.v \
+	$(CORE_TREE)/platform/alpha/rtl/clkmgr_reset_gen.v \
+	$(CORE_TREE)/platform/common/extra/reset_replicator.v \
+	$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
+	$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
+	$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
+	$(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
+
+# Verilog files selected by the core configuration script.
+
+-include ./core_vfiles.mk
+
+# List of Vivado's intermediate files and helper files
+
+junk = \
+	$(tcl_create_project) \
+	$(tcl_run_synthesis) \
+	$(tcl_run_implementation) \
+	$(tcl_generate_bitstream) \
+	$(project).*/ \
+	usage_statistics_webtalk.xml\
+	.Xil/
+
+
+
+.PHONY: all clean distclean
+
+# default target is to build a bitstream
+
+all: $(top_module).bit
+
+# recipe to generate "xilinx project" (.xpr) file
+
+$(project).xpr:
+	# create helper tcl file
+	echo "# $(tcl_warning_message)" > $(tcl_create_project)
+	# add create_project command
+	echo "create_project -force -part $(part) $(project)" >> $(tcl_create_project)
+	# add sources and constraints
+	for z in $(vfiles); do echo "add_files -fileset $(proj_sources_set) $$z" >> $(tcl_create_project); done
+	for z in $(xdcfiles); do echo "add_files -fileset $(proj_constraints_set) $$z" >> $(tcl_create_project); done
+	# add include directories
+	echo "set_property include_dirs {$(vlogincdirs)} [get_filesets $(proj_sources_set)]" >> $(tcl_create_project)
+	# invoke vivado
+	vivado -mode batch $(vivado_options) -source $(tcl_create_project)
+
+# recipe to run synthesis, this should produce "design check point" (.dcp) file
+
+$(synth_run)/$(top_module).dcp: $(project).xpr $(vfiles) $(xdcfiles)
+	# create helper tcl file
+	echo "# $(tcl_warning_message)" > $(tcl_run_synthesis)
+	# add open_project command
+	echo "open_project $(project).xpr" >> $(tcl_run_synthesis)
+	# reset synthesis run
+	echo "reset_run $(proj_synthesis_run)" >> $(tcl_run_synthesis)
+	# launch synthesis run and wait for it to finish
+	echo "launch_runs $(proj_synthesis_run)" >> $(tcl_run_synthesis)
+	echo "wait_on_run $(proj_synthesis_run)" >> $(tcl_run_synthesis)
+	# invoke vivado
+	vivado -mode batch $(vivado_options) -source $(tcl_run_synthesis)
+	# for some reason vivado seems to overwrite the project file when exiting,
+	# which causes .xpr to appear newer, than the corresponding .dcp and gets
+	# make to always re-run synthesis, even if the .dcp is already available
+	# the quick and dirty workaround is to clone the .dcp's date to .xpr
+	touch -r $(synth_run)/$(top_module).dcp $(project).xpr
+
+# recipe to run implementation, this should produce another routed "design check point" (.dcp) file
+
+$(impl_run)/$(top_module)_routed.dcp: $(synth_run)/$(top_module).dcp
+	# create helper tcl file
+	echo "# $(tcl_warning_message)" > $(tcl_run_implementation)
+	# add open_project command
+	echo "open_project $(project).xpr" >> $(tcl_run_implementation)
+	# reset synthesis run
+	echo "reset_run $(proj_implementation_run)" >> $(tcl_run_implementation)
+	# launch synthesis run and wait for it to finish
+	echo "launch_runs $(proj_implementation_run)" >> $(tcl_run_implementation)
+	echo "wait_on_run $(proj_implementation_run)" >> $(tcl_run_implementation)
+	# invoke vivado
+	vivado -mode batch $(vivado_options) -source $(tcl_run_implementation)
+	# same thing as for synthesis, counteract vivado's stupid project file overwriting
+	touch -r $(synth_run)/$(top_module).dcp $(project).xpr
+
+# recipe to build the bitstream (.bit) from routed checkpoint
+
+$(top_module).bit: $(impl_run)/$(top_module)_routed.dcp
+	# create helper tcl file
+	echo "# $(tcl_warning_message)" > $(tcl_generate_bitstream)
+	# add open_project command
+	echo "open_project $(project).xpr" >> $(tcl_generate_bitstream)
+	# add open_run command
+	echo "open_run $(proj_implementation_run)" >> $(tcl_generate_bitstream)
+	# enable compression
+	echo "set_property BITSTREAM.GENERAL.COMPRESS TRUE [get_designs $(proj_implementation_run)]" >> $(tcl_generate_bitstream)
+	# add write_bitstream command
+	echo "write_bitstream -force $(top_module).bit" >> $(tcl_generate_bitstream)
+	# invoke vivado
+	vivado -mode batch $(vivado_options) -source $(tcl_generate_bitstream)
+	# same thing as for synthesis and implementation, counteract vivado's stupid project file overwriting
+	touch -r $(synth_run)/$(top_module).dcp $(project).xpr
+
+# Build the default core_selector if it doesn't already exist.
+
+core_selector.v core_vfiles.mk:
+	$(CONFIG_GEN) -p $(CONFIG_PROJECT)
+
+# clean
+clean: 
+	rm -rf $(junk)
+
+distclean: clean
+	rm core_selector.v core_vfiles.mk