diff options
| -rw-r--r-- | build/Makefile | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/build/Makefile b/build/Makefile index 050789a..ea8d032 100644 --- a/build/Makefile +++ b/build/Makefile @@ -1,6 +1,6 @@ # Localize all the relative path awfulness in one variable. -CORE_TREE := $(abspath ../../../..) +CORE_TREE := $(abspath ../../..) # Figure out what the native word size is on the build host, because # the XiLinx tools care for some reason. @@ -47,10 +47,10 @@ rsa: # Verilog files that always go with builds on this platform. vfiles = \ - $(CORE_TREE)/platform/alpha/fmc/rtl/alpha_fmc_top.v \ - $(CORE_TREE)/platform/alpha/common/rtl/alpha_regs.v \ - $(CORE_TREE)/platform/alpha/common/rtl/alpha_clkmgr.v \ - $(CORE_TREE)/platform/alpha/common/rtl/clkmgr_dcm.v \ + $(CORE_TREE)/platform/alpha/rtl/alpha_fmc_top.v \ + $(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \ + $(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \ + $(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \ ./core_selector.v \ $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \ @@ -83,4 +83,4 @@ distclean: clean VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME lint: - verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/alpha/common/rtl/lint-dummy.v + verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/alpha/rtl/lint-dummy.v |