Out of curiosity I tried compiling the bitstream with Vivado. These constraintsfmc_clk_core

may come handy if you're brave enough to try this at home.

3 files changed, 102 insertions, 0 deletions

diff --git a/xdc/alpha_fmc_clocks.xdc b/xdc/alpha_fmc_clocks.xdc
new file mode 100644
index 0000000..4184ff4
--- /dev/null
+++ b/xdc/alpha_fmc_clocks.xdc
@@ -0,0 +1 @@
+create_clock -period 22.222 -name clk_fmc -waveform {0.000 11.111} [get_ports fmc_clk]
diff --git a/xdc/alpha_fmc_pinout.xdc b/xdc/alpha_fmc_pinout.xdc
new file mode 100644
index 0000000..9f4e08a
--- /dev/null
+++ b/xdc/alpha_fmc_pinout.xdc
@@ -0,0 +1,100 @@
+set_property PACKAGE_PIN "U3"   [get_ports {led_pins[0]}]
+set_property PACKAGE_PIN "T1"   [get_ports {led_pins[1]}]
+set_property PACKAGE_PIN "W22"  [get_ports {led_pins[2]}]
+set_property PACKAGE_PIN "AA20" [get_ports {led_pins[3]}]
+
+set_property PACKAGE_PIN "W11"  [get_ports {fmc_clk    }]
+set_property PACKAGE_PIN "V5"   [get_ports {fmc_ne1    }]
+set_property PACKAGE_PIN "W16"  [get_ports {fmc_noe    }]
+set_property PACKAGE_PIN "AA6"  [get_ports {fmc_nwe    }]
+set_property PACKAGE_PIN "W17"  [get_ports {fmc_nl     }]
+set_property PACKAGE_PIN "Y6"   [get_ports {fmc_nwait  }]
+
+set_property PACKAGE_PIN "Y17"  [get_ports {fmc_a[0]}]
+set_property PACKAGE_PIN "AB16" [get_ports {fmc_a[1]}]
+set_property PACKAGE_PIN "AA16" [get_ports {fmc_a[2]}]
+set_property PACKAGE_PIN "Y16"  [get_ports {fmc_a[3]}]
+set_property PACKAGE_PIN "AB17" [get_ports {fmc_a[4]}]
+set_property PACKAGE_PIN "AA13" [get_ports {fmc_a[5]}]
+set_property PACKAGE_PIN "AB13" [get_ports {fmc_a[6]}]
+set_property PACKAGE_PIN "AA15" [get_ports {fmc_a[7]}]
+set_property PACKAGE_PIN "AB15" [get_ports {fmc_a[8]}]
+set_property PACKAGE_PIN "Y13"  [get_ports {fmc_a[9]}]
+set_property PACKAGE_PIN "AA14" [get_ports {fmc_a[10]}]
+set_property PACKAGE_PIN "Y14"  [get_ports {fmc_a[11]}]
+set_property PACKAGE_PIN "AB10" [get_ports {fmc_a[12]}]
+set_property PACKAGE_PIN "V2"   [get_ports {fmc_a[13]}]
+set_property PACKAGE_PIN "AB12" [get_ports {fmc_a[14]}]
+set_property PACKAGE_PIN "AB8"  [get_ports {fmc_a[15]}]
+set_property PACKAGE_PIN "AA9"  [get_ports {fmc_a[16]}]
+set_property PACKAGE_PIN "AA8"  [get_ports {fmc_a[17]}]
+set_property PACKAGE_PIN "Y7"   [get_ports {fmc_a[18]}]
+set_property PACKAGE_PIN "AB21" [get_ports {fmc_a[19]}]
+set_property PACKAGE_PIN "AB22" [get_ports {fmc_a[20]}]
+set_property PACKAGE_PIN "AB20" [get_ports {fmc_a[21]}]
+set_property PACKAGE_PIN "Y21"  [get_ports {fmc_a[22]}]
+set_property PACKAGE_PIN "Y22"  [get_ports {fmc_a[23]}]
+#set_property PACKAGE_PIN "AB18" [get_ports {fmc_a[24]}]
+#set_property PACKAGE_PIN "AA19" [get_ports {fmc_a[25]}]
+
+set_property PACKAGE_PIN "AB7"  [get_ports {fmc_d[0]}]
+set_property PACKAGE_PIN "AB6"  [get_ports {fmc_d[1]}]
+set_property PACKAGE_PIN "U1"   [get_ports {fmc_d[2]}]
+set_property PACKAGE_PIN "U2"   [get_ports {fmc_d[3]}]
+set_property PACKAGE_PIN "AB11" [get_ports {fmc_d[4]}]
+set_property PACKAGE_PIN "AA11" [get_ports {fmc_d[5]}]
+set_property PACKAGE_PIN "Y11"  [get_ports {fmc_d[6]}]
+set_property PACKAGE_PIN "Y12"  [get_ports {fmc_d[7]}]
+set_property PACKAGE_PIN "Y18"  [get_ports {fmc_d[8]}]
+set_property PACKAGE_PIN "AA21" [get_ports {fmc_d[9]}]
+set_property PACKAGE_PIN "W20"  [get_ports {fmc_d[10]}]
+set_property PACKAGE_PIN "N15"  [get_ports {fmc_d[11]}]
+set_property PACKAGE_PIN "U20"  [get_ports {fmc_d[12]}]
+set_property PACKAGE_PIN "AA1"  [get_ports {fmc_d[13]}]
+set_property PACKAGE_PIN "AB1"  [get_ports {fmc_d[14]}]
+set_property PACKAGE_PIN "AB2"  [get_ports {fmc_d[15]}]
+set_property PACKAGE_PIN "AB3"  [get_ports {fmc_d[16]}]
+set_property PACKAGE_PIN "Y3"   [get_ports {fmc_d[17]}]
+set_property PACKAGE_PIN "AA3"  [get_ports {fmc_d[18]}]
+set_property PACKAGE_PIN "AA5"  [get_ports {fmc_d[19]}]
+set_property PACKAGE_PIN "AB5"  [get_ports {fmc_d[20]}]
+set_property PACKAGE_PIN "Y4"   [get_ports {fmc_d[21]}]
+set_property PACKAGE_PIN "AA4"  [get_ports {fmc_d[22]}]
+set_property PACKAGE_PIN "V4"   [get_ports {fmc_d[23]}]
+set_property PACKAGE_PIN "W10"  [get_ports {fmc_d[24]}]
+set_property PACKAGE_PIN "R4"   [get_ports {fmc_d[25]}]
+set_property PACKAGE_PIN "W12"  [get_ports {fmc_d[26]}]
+set_property PACKAGE_PIN "W14"  [get_ports {fmc_d[27]}]
+set_property PACKAGE_PIN "V20"  [get_ports {fmc_d[28]}]
+set_property PACKAGE_PIN "V18"  [get_ports {fmc_d[29]}]
+set_property PACKAGE_PIN "R21"  [get_ports {fmc_d[30]}]
+set_property PACKAGE_PIN "P21"  [get_ports {fmc_d[31]}]
+
+set_property PACKAGE_PIN "W19"  [get_ports {ct_noise}]
+
+set_property PACKAGE_PIN "V3"   [get_ports {mkm_sclk}]
+set_property PACKAGE_PIN "W2"   [get_ports {mkm_cs_n}]
+set_property PACKAGE_PIN "W1"   [get_ports {mkm_di}]
+set_property PACKAGE_PIN "Y1"   [get_ports {mkm_do}]
+
+
+set_property IOSTANDARD "LVCMOS33" [get_ports {led_*}]
+set_property IOSTANDARD "LVCMOS33" [get_ports {fmc_*}]
+set_property IOSTANDARD "LVCMOS33" [get_ports {ct_noise}]
+set_property IOSTANDARD "LVCMOS33" [get_ports {mkm_*}]
+
+
+set_property DRIVE 8 [get_ports {led_pins[*]}]
+set_property DRIVE 8 [get_ports {fmc_nwait}]
+set_property DRIVE 8 [get_ports {fmc_d[*]}]
+set_property DRIVE 8 [get_ports {mkm_sclk}]
+set_property DRIVE 8 [get_ports {mkm_cs_n}]
+set_property DRIVE 8 [get_ports {mkm_di}]
+
+
+set_property SLEW "SLOW" [get_ports {led_pins[*]}]
+set_property SLEW "FAST" [get_ports {fmc_nwait}]
+set_property SLEW "FAST" [get_ports {fmc_d[*]}]
+set_property SLEW "SLOW" [get_ports {mkm_sclk}]
+set_property SLEW "SLOW" [get_ports {mkm_cs_n}]
+set_property SLEW "SLOW" [get_ports {mkm_di}]
diff --git a/xdc/alpha_fmc_timing.xdc b/xdc/alpha_fmc_timing.xdc
new file mode 100644
index 0000000..e311270
--- /dev/null
+++ b/xdc/alpha_fmc_timing.xdc
@@ -0,0 +1 @@
+create_clock -period 22.222 -name clk_fmc -waveform {0.000 11.111} [get_ports clk_fmc]