diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-06-14 09:48:28 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-06-14 09:48:28 +0200 |
| commit | f34e44c3b2db29ad536e6c4a6792fbb7c0581164 (patch) | |
| tree | bcd05b58fdd161b8f0283cd77976ccad5e692333 /ucf | |
| parent | a4e91b6221f75045dd1d97362e9d12c590ebc15a (diff) | |
(1) Added ports and constraints for the gpio banks connected to the FPGA. (2) Added toggle circuit that generates a divided down version of the internal sys_clk. This divided clock is presented on pin 0 of both gpio banks.
Diffstat (limited to 'ucf')
| -rw-r--r-- | ucf/alpha_fmc.ucf | 36 |
1 files changed, 27 insertions, 9 deletions
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf index 5e71c64..9ed68fd 100644 --- a/ucf/alpha_fmc.ucf +++ b/ucf/alpha_fmc.ucf @@ -55,15 +55,33 @@ TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%; #------------------------------------------------------------------------------- # FPGA Pinout #------------------------------------------------------------------------------- -#
-NET "led_pins<0>" LOC = "U3"; -NET "led_pins<1>" LOC = "T1"; -NET "led_pins<2>" LOC = "W22"; -NET "led_pins<3>" LOC = "AA20"; -# -NET "led_pins<*>" IOSTANDARD = "LVCMOS33"; -NET "led_pins<*>" SLEW = SLOW; -NET "led_pins<*>" DRIVE = 8; +# LEDs +NET "led_pins<0>" LOC = "U3" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8; +NET "led_pins<1>" LOC = "T1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8; +NET "led_pins<2>" LOC = "W22" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8; +NET "led_pins<3>" LOC = "AA20" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8; + + +# GPIOs. Two banks +NET "fpga_gpio_a0" LOC = "C15" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a1" LOC = "E13" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a2" LOC = "E14" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a3" LOC = "E16" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a4" LOC = "D16" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a5" LOC = "D14" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a6" LOC = "D15" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_a7" LOC = "B15" | IOSTANDARD = "LVCMOS33" ; + +NET "fpga_gpio_b0" LOC = "B16" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b1" LOC = "C13" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b2" LOC = "B13" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b3" LOC = "A15" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b4" LOC = "A16" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b5" LOC = "A13" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b6" LOC = "A14" | IOSTANDARD = "LVCMOS33" ; +NET "fpga_gpio_b7" LOC = "B17" | IOSTANDARD = "LVCMOS33" ; + + # NET "gclk_pin" LOC = "D17" | IOSTANDARD = "LVCMOS33" ; # |