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authorPaul Selkirk <paul@psgd.org>2018-08-27 16:59:34 -0400
committerPaul Selkirk <paul@psgd.org>2019-04-09 17:13:11 -0400
commit97aaac4da6e33e218b26c1963ab563e9e2c11e82 (patch)
treec3596b358e16f0a09fd34c82d0cbb851420996b2 /build/Makefile
parentab23f87e78f441830587c6c82d90e35b4cec7d29 (diff)
correct fpga part number, add keywrap build target
Diffstat (limited to 'build/Makefile')
-rw-r--r--build/Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile
index ca5d735..22fd1f4 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -40,6 +40,10 @@ bare trng hash mkmif rsa hsm hsm-super:
$(CONFIG_GEN) -p $@
$(MAKE) project=$(project)_$@ ucf=$(ucf)
+keywrap:
+ $(CONFIG_GEN) -p keywrap
+ $(MAKE) project=$(project)_keywrap ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \