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authorPaul Selkirk <paul@psgd.org>2019-01-22 19:39:09 -0500
committerPaul Selkirk <paul@psgd.org>2019-01-22 20:15:26 -0500
commit516b2975958b05c72f573c37c075e5793c514101 (patch)
treeded6ab7cc8e02729e3e444c058c9ee8fd766ffa1 /build/Makefile
parentf01086416f290352c2c9faa0f1c6b1fce31e8f01 (diff)
Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0
(which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile.
Diffstat (limited to 'build/Makefile')
-rw-r--r--build/Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile
index f573ace..60e55f9 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
+# Verilog include directories, if needed
+
+vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
all: $(project).bit
# Build the default core_selector if it doesn't already exist.