From 516b2975958b05c72f573c37c075e5793c514101 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 22 Jan 2019 19:39:09 -0500 Subject: Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0 (which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile. --- build/Makefile | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'build/Makefile') diff --git a/build/Makefile b/build/Makefile index f573ace..60e55f9 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. -- cgit v1.2.3