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| author | Paul Selkirk <paul@psgd.org> | 2019-01-22 19:39:09 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2019-01-22 19:52:04 -0500 |
| commit | a69ef3c13244c5269a1ad1a48fdc736493005975 (patch) | |
| tree | f4724002906f3443d39bcb8ccab5275901ca8f9f | |
| parent | 6134800a26c31595b648200195e188eebfa72dbb (diff) | |
Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0fmc_clk
(which he only committed on fmc_clk, and I was only looking at master).
But I moved the curly brackets from Makefile to xilinx.mk, because
a) Makefile shouldn't need to know the picky details of xst option
syntax, and
b) xst will throw an uninformative error if called with '-vlgincdir '
versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile.
| -rw-r--r-- | build/Makefile | 6 | ||||
| -rw-r--r-- | build/xilinx.mk | 2 | ||||
| -rw-r--r-- | build/xilinx.opt | 1 |
3 files changed, 4 insertions, 5 deletions
diff --git a/build/Makefile b/build/Makefile index 5a6107d..60e55f9 100644 --- a/build/Makefile +++ b/build/Makefile @@ -16,11 +16,11 @@ part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf ?= ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf -# verilog include directories {yes, XST wants them exactly this way in curly braces} -vlgincdir = {$(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode} +# Verilog include directories, if needed +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode all: $(project).bit diff --git a/build/xilinx.mk b/build/xilinx.mk index c88f00b..4bfefde 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -154,8 +154,8 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ + echo "-vlgincdir {$(vlgincdir)}" >> $@ cat ./xilinx.opt $(optfile) >> $@ - echo "-vlgincdir $(vlgincdir)" >> $@ junk += $(project).scr $(project).post_map.twr: $(project).ncd diff --git a/build/xilinx.opt b/build/xilinx.opt index 933f7df..1ac8957 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -45,4 +45,3 @@ -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 --vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode} |