path: root/rtl/alpha_clkmgr.v

//======================================================================
//
// alpha_clkmgr.v
// ---------------
// Clock and reset implementation for the Cryptech Alpha
// FPGA framework.
//
//
// Author: Pavel Shatov
// Copyright (c) 2016, 2018-2019 NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module alpha_clkmgr
(
    input wire  fmc_clk,    // signal from clock pin

    output wire io_clk,     // buffered i/o clock
    output wire sys_clk,    // buffered system clock output
    output wire sys_rst_n,  // system reset output (async set, sync clear, active-low)
    output wire core_clk    // buffered high speed core clock
);


    //
    // Parameters
    //
    parameter integer CLK_CORE_MULT = 4;
    

    //
    // STARTUPE2
    //
    wire cfg_mclk;  // 65 MHz (+/- 50%) internal oscillator
    wire cfg_eos;   // end-of-startup flag
    
    STARTUPE2 #
    (
        .SIM_CCLK_FREQ  (0.0),    // config clock frequency for simulation
        .PROG_USR       ("FALSE") // only used with encrypted bitstreams
    )
    STARTUPE2_inst
    (
        .CLK        (1'b0),     // no external clock
        .CFGCLK     (),         // config clock (unused)
        .CFGMCLK    (cfg_mclk), // config clock
        .EOS        (cfg_eos),  // end-of-startup flag

        .USRCCLKO   (1'b0),     // custom clock for configuration memory access (unused)
        .USRCCLKTS  (1'b0),     // UG470 recommends this to be held low
        .USRDONEO   (1'b1),     // custom value to drive onto DONE pin (unused)
        .USRDONETS  (1'b1),     // tri-state DONE pin (unused)

        .GSR        (1'b0),     // UG470 recommends hardwiring this low
        .GTS        (1'b0),     // UG470 recommends this to be tied low
        
        .PREQ       (),         // unused when PROG_USR is disabled
        .PACK       (1'b0),     // only used when PROG_USR is enabled

        .KEYCLEARB  (1'b1)      // unused
    );


    //
    // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
    //
    wire mmcm_reset;  // reset input
    wire mmcm_locked; // output clock valid

    clkmgr_mmcm #
    (
        .CLK_CORE_MULT(CLK_CORE_MULT)
    )
    mmcm_inst
    (
        .fmc_clk_in   (fmc_clk),
        .rst_in       (mmcm_reset),

        .io_clk_out   (io_clk),
        .sys_clk_out  (sys_clk),
        .core_clk_out (core_clk),
        .locked_out   (mmcm_locked)
    );

    //
    // MMCM Controller
    //
    clkmgr_mmcm_ctrl mmcm_ctrl_inst
    (
        .clk_in         (cfg_mclk),
        .reset_n_in     (cfg_eos),
        .locked_in      (mmcm_locked),
        .reset_out      (mmcm_reset)
    );
    

    //
    // System Reset Logic
    //
    clkmgr_reset_gen #(.SHREG_WIDTH(16)) reset_gen_inst
    (
        .clk_in         (sys_clk),
        .locked_in      (mmcm_locked),
        .reset_n_out    (sys_rst_n)
    );


endmodule


//======================================================================
// EOF alpha_clkmgr.v
//======================================================================