1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
|
//------------------------------------------------------------------------------
//
// tb_modular_multiplier.v
// -----------------------------------------------------------------------------
// Testbench for Curve25519 modular multiplier.
//
// Authors: Pavel Shatov
//
// Copyright (c) 2018, NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//------------------------------------------------------------------------------
module tb_modular_multiplier;
//
// Test Vectors
//
localparam A1 = 256'h216936d3_cd6e53fe_c0a4e231_fdd6dc5c_692cc760_9525a7b2_c9562d60_8f25d51a; // GX
localparam B1 = 256'h66666666_66666666_66666666_66666666_66666666_66666666_66666666_66666658; // GY
//
// Core Parameters
//
localparam WORD_COUNTER_WIDTH = 3;
localparam OPERAND_NUM_WORDS = 8;
//
// Clock (100 MHz)
//
`define CLOCK_PERIOD 10.0
`define CLOCK_HALF_PERIOD (0.5 * `CLOCK_PERIOD)
reg clk = 1'b0;
always #`CLOCK_HALF_PERIOD clk = ~clk;
//
// Inputs, Outputs
//
reg rst_n;
reg ena;
wire rdy;
//
// Buffers (A, B, P)
//
wire [WORD_COUNTER_WIDTH-1:0] core_a_addr;
wire [WORD_COUNTER_WIDTH-1:0] core_b_addr;
wire [WORD_COUNTER_WIDTH-1:0] core_p_addr;
wire core_p_wren;
wire [ 32-1:0] core_a_data;
wire [ 32-1:0] core_b_data;
wire [ 32-1:0] core_p_data;
reg [WORD_COUNTER_WIDTH-1:0] tb_ab_addr;
reg [WORD_COUNTER_WIDTH-1:0] tb_p_addr;
reg tb_ab_wren;
reg [ 32-1:0] tb_a_data;
reg [ 32-1:0] tb_b_data;
wire [ 32-1:0] tb_p_data;
bram_1rw_1ro_readfirst # (.MEM_WIDTH(32), .MEM_ADDR_BITS(WORD_COUNTER_WIDTH))
bram_a
( .clk(clk),
.a_addr(tb_ab_addr), .a_wr(tb_ab_wren), .a_in(tb_a_data), .a_out(),
.b_addr(core_a_addr), .b_out(core_a_data)
);
bram_1rw_1ro_readfirst # (.MEM_WIDTH(32), .MEM_ADDR_BITS(WORD_COUNTER_WIDTH))
bram_b
( .clk(clk),
.a_addr(tb_ab_addr), .a_wr(tb_ab_wren), .a_in(tb_b_data), .a_out(),
.b_addr(core_b_addr), .b_out(core_b_data)
);
bram_1rw_1ro_readfirst # (.MEM_WIDTH(32), .MEM_ADDR_BITS(WORD_COUNTER_WIDTH))
bram_p
( .clk(clk),
.a_addr(core_p_addr), .a_wr(core_p_wren), .a_in(core_p_data), .a_out(),
.b_addr(tb_p_addr), .b_out(tb_p_data)
);
//
// UUT
//
ed25519_modular_multiplier uut
(
.clk (clk),
.rst_n (rst_n),
.ena (ena),
.rdy (rdy),
.a_addr (core_a_addr),
.b_addr (core_b_addr),
.p_addr (core_p_addr),
.p_wren (core_p_wren),
.a_din (core_a_data),
.b_din (core_b_data),
.p_dout (core_p_data)
);
//
// Testbench Routine
//
reg ok = 1;
initial begin
/* initialize control inputs */
rst_n = 0;
ena = 0;
/* wait for some time */
#200;
/* de-assert reset */
rst_n = 1;
/* wait for some time */
#100;
/* run tests */
$display("1. A1*B1=P1...");
test_modular_multiplier(A1, B1);
/* print result */
if (ok) $display("tb_modular_multiplier: SUCCESS");
else $display("tb_modular_multiplier: FAILURE");
//
#10000;
//
//$finish;
//
end
//
// Test Task
//
task test_modular_multiplier;
input [255:0] a;
input [255:0] b;
reg [255:0] a_shreg;
reg [255:0] b_shreg;
reg [255:0] p_shreg;
reg p_ok;
integer w;
begin
/* initialize result */
p_ok = 0;
/* initialize shift registers */
a_shreg = a;
b_shreg = b;
/* start filling memories */
tb_ab_wren = 1;
/* write all the words */
for (w=0; w<OPERAND_NUM_WORDS; w=w+1) begin
/* set addresses */
tb_ab_addr = w[WORD_COUNTER_WIDTH-1:0];
/* set data words */
tb_a_data = a_shreg[31:0];
tb_b_data = b_shreg[31:0];
/* shift inputs */
a_shreg = {{32{1'bX}}, a_shreg[255:32]};
b_shreg = {{32{1'bX}}, b_shreg[255:32]};
/* wait for 1 clock tick */
#`CLOCK_PERIOD;
end
/* stop filling memories */
tb_ab_wren = 0;
/* wipe addresses */
tb_ab_addr = {WORD_COUNTER_WIDTH{1'bX}};
/* wipe data words */
tb_a_data = {32{1'bX}};
tb_b_data = {32{1'bX}};
/* start operation */
ena = 1;
/* clear flag */
#`CLOCK_PERIOD ena = 0;
/* wait for operation to complete */
while (!rdy) #`CLOCK_PERIOD;
// /* read result */
// for (w=0; w<OPERAND_NUM_WORDS; w=w+1) begin
//
// /* set address */
// tb_qxy_addr = w[WORD_COUNTER_WIDTH-1:0];
//
// /* wait for 1 clock tick */
// #10;
//
// /* store data word */
// qx_shreg = {tb_qx_data, qx_shreg[255:32]};
// qy_shreg = {tb_qy_data, qy_shreg[255:32]};
//
// end
//
// /* compare */
// q_ok = (qx_shreg == qx) &&
// (qy_shreg == qy);
//
/* display results */
if (p_ok) $display("test_modular_multiplier(): CORRECT RESULT");
else $display("test_modular_multiplier(): WRONG RESULT");
/* update global flag */
ok = ok & p_ok;
end
endtask
endmodule
//------------------------------------------------------------------------------
// End-of-File
//------------------------------------------------------------------------------
|
