diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-11-09 18:04:42 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-11-09 18:04:42 +0300 |
| commit | 4cfb1909d20f7cef0feaaa41ee1486fa56bbe4a3 (patch) | |
| tree | abc97c4ad37f2e5f417b23a024e69870474bad2e | |
| parent | b9ea65597d951bba7602a93e0205342ab50e4d95 (diff) | |
* Cleaned up to remove synthesis warnings
* Optimized double/single modulus switching, got rid of some warnings as a
side effect
* Switched to primitives from core/lib/
| -rw-r--r-- | rtl/ed25519_uop_worker.v | 51 |
1 files changed, 35 insertions, 16 deletions
diff --git a/rtl/ed25519_uop_worker.v b/rtl/ed25519_uop_worker.v index 244ff97..a483961 100644 --- a/rtl/ed25519_uop_worker.v +++ b/rtl/ed25519_uop_worker.v @@ -140,7 +140,7 @@ module ed25519_uop_worker wire [ 32-1:0] mw_mover_y_dout; wire mw_mover_y_wren; - mw_mover # + multiword_mover # ( .WORD_COUNTER_WIDTH (WORD_COUNTER_WIDTH), .OPERAND_NUM_WORDS (OPERAND_NUM_WORDS) @@ -173,7 +173,7 @@ module ed25519_uop_worker wire [ 32-1:0] mod_mul_p_dout; wire mod_mul_p_wren; - ed25519_modular_multiplier mod_mul_inst + curve25519_modular_multiplier mod_mul_inst ( .clk (clk), .rst_n (rst_n), @@ -200,11 +200,11 @@ module ed25519_uop_worker wire [WORD_COUNTER_WIDTH-1:0] mod_add_s_addr; wire [ 32-1:0] mod_add_a_din; wire [ 32-1:0] mod_add_b_din; - reg [ 32-1:0] mod_add_n_din; + wire [ 32-1:0] mod_add_n_din; wire [ 32-1:0] mod_add_s_dout; wire mod_add_s_wren; - mod_adder # + modular_adder # ( .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) @@ -237,11 +237,11 @@ module ed25519_uop_worker wire [WORD_COUNTER_WIDTH-1:0] mod_sub_d_addr; wire [ 32-1:0] mod_sub_a_din; wire [ 32-1:0] mod_sub_b_din; - reg [ 32-1:0] mod_sub_n_din; + wire [ 32-1:0] mod_sub_n_din; wire [ 32-1:0] mod_sub_d_dout; wire mod_sub_d_wren; - mod_subtractor # + modular_subtractor # ( .OPERAND_NUM_WORDS(OPERAND_NUM_WORDS), .WORD_COUNTER_WIDTH(WORD_COUNTER_WIDTH) @@ -264,18 +264,36 @@ module ed25519_uop_worker // - // Double Modulus + // Double/Single Modulus // + reg mod_sub_n_bit_lower; + + reg mod_add_n_bit_upper; + reg mod_add_n_bit_lower0; + reg mod_add_n_bit_lower1; + + assign mod_sub_n_din = {{26{1'b1}}, + mod_sub_n_bit_lower, 2'b11, mod_sub_n_bit_lower, 1'b1, mod_sub_n_bit_lower}; + + assign mod_add_n_din = {mod_add_n_bit_upper, {25{1'b1}}, + mod_add_n_bit_lower0, mod_add_n_bit_lower1, 1'b1, mod_add_n_bit_lower0, mod_add_n_bit_lower1, mod_add_n_bit_lower0}; + always @(posedge clk) begin // case (mod_add_n_addr) + 3'd0: {mod_add_n_bit_upper, mod_add_n_bit_lower1, mod_add_n_bit_lower0} <= !final_reduce ? 3'b110 : 3'b101; //32'hFFFFFFDA : 32'hFFFFFFED; + 3'd7: {mod_add_n_bit_upper, mod_add_n_bit_lower1, mod_add_n_bit_lower0} <= !final_reduce ? 3'b111 : 3'b011; //32'hFFFFFFFF : 32'h7FFFFFFF; + default: {mod_add_n_bit_upper, mod_add_n_bit_lower1, mod_add_n_bit_lower0} <= 3'b111; + endcase + /* + case (mod_add_n_addr) 3'd0: mod_add_n_din <= !final_reduce ? 32'hFFFFFFDA : 32'hFFFFFFED; 3'd7: mod_add_n_din <= !final_reduce ? 32'hFFFFFFFF : 32'h7FFFFFFF; default: mod_add_n_din <= 32'hFFFFFFFF; endcase - // - if (mod_sub_n_addr == 3'd0) mod_sub_n_din <= 32'hFFFFFFDA; - else mod_sub_n_din <= 32'hFFFFFFFF; + */ + if (mod_sub_n_addr == 3'd0) mod_sub_n_bit_lower <= 1'b0; + else mod_sub_n_bit_lower <= 1'b1; // end @@ -367,7 +385,7 @@ module ed25519_uop_worker UOP_OPCODE_COPY: begin // banks_src1_addr = mw_mover_x_addr; - banks_src2_addr = 'bX; + banks_src2_addr = {3{1'bX}}; // banks_dst_addr = mw_mover_y_addr; // @@ -418,14 +436,15 @@ module ed25519_uop_worker // default: begin // - banks_src1_addr = 'bX; - banks_src2_addr = 'bX; + banks_src1_addr = {3{1'bX}}; + banks_src2_addr = {3{1'bX}}; + // + banks_dst_addr = {3{1'bX}}; // - banks_dst_addr = 'bX; + banks_dst_wren = 1'b0; // - banks_dst_wren = 'b0; + banks_dst_din = {32{1'bX}}; // - banks_dst_din = 'bX; end // endcase |