//======================================================================
//
// Copyright (c) 2018, NORDUnet A/S All rights reserved.
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//
//======================================================================`timescale 1ns 1ps
module ed25519_microcode
(
input wire clk,
input wire [UOP_ADDR_WIDTH-1:0] addr,
output reg [UOP_DATA_WIDTH-1:0] data
);
`include "ed25519_uop.v"
always @(posedge clk)
//
case (addr)
// Initialization
6'd00: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X};
6'd01: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y};
6'd02: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z};
6'd03: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T};
6'd04: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X};
6'd05: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y};
6'd06: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z};
6'd07: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T};
6'd08: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE};
// Before Round when k = 1
6'd09: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X};
6'd10: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y};
6'd11: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z};
6'd12: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T};
6'd13: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X};
6'd14: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y};
6'd15: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z};
6'd16: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T};
6'd17: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE};
// Before Round when k = 0
6'd18: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X};
6'd19: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y};
6'd20: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z};
6'd21: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T};
6'd22: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X};
6'd23: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y};
6'd24: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z};
6'd25: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T};
6'd26: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE};
endcase
endmodule
