1 files changed, 24 insertions, 24 deletions

diff --git a/rtl/curve/rom/brom_p384_h_y.v b/rtl/curve/rom/brom_p384_h_y.v
index 98c59ed..c390e3d 100644
--- a/rtl/curve/rom/brom_p384_h_y.v
+++ b/rtl/curve/rom/brom_p384_h_y.v
@@ -33,39 +33,39 @@
 `timescale 1ns / 1ps
 
 module brom_p384_h_y
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-

+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			4'b0000:	bram_reg_b <= 32'h6f15f19d;

-			4'b0001:	bram_reg_b <= 32'h85bce284;

-			4'b0010:	bram_reg_b <= 32'he2817e62;

-			4'b0011:	bram_reg_b <= 32'hf59f4e30;

-			4'b0100:	bram_reg_b <= 32'h4a0f473e;

-			4'b0101:	bram_reg_b <= 32'h1625ceec;

-			4'b0110:	bram_reg_b <= 32'hd765eb83;

-			4'b0111:	bram_reg_b <= 32'h070be242;

-			4'b1000:	bram_reg_b <= 32'h6d6d23d6;

-			4'b1001:	bram_reg_b <= 32'ha2616740;

-			4'b1010:	bram_reg_b <= 32'h69d9d390;

-			4'b1011:	bram_reg_b <= 32'hc9e821b5;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h6f15f19d;
+       4'b0001:	bram_reg_b <= 32'h85bce284;
+       4'b0010:	bram_reg_b <= 32'he2817e62;
+       4'b0011:	bram_reg_b <= 32'hf59f4e30;
+       4'b0100:	bram_reg_b <= 32'h4a0f473e;
+       4'b0101:	bram_reg_b <= 32'h1625ceec;
+       4'b0110:	bram_reg_b <= 32'hd765eb83;
+       4'b0111:	bram_reg_b <= 32'h070be242;
+       4'b1000:	bram_reg_b <= 32'h6d6d23d6;
+       4'b1001:	bram_reg_b <= 32'ha2616740;
+       4'b1010:	bram_reg_b <= 32'h69d9d390;
+       4'b1011:	bram_reg_b <= 32'hc9e821b5;
+     endcase
 
 endmodule