1 files changed, 23 insertions, 23 deletions

diff --git a/rtl/curve/rom/brom_p384_h_x.v b/rtl/curve/rom/brom_p384_h_x.v
index a6c474e..b6a0886 100644
--- a/rtl/curve/rom/brom_p384_h_x.v
+++ b/rtl/curve/rom/brom_p384_h_x.v
@@ -33,39 +33,39 @@
 `timescale 1ns / 1ps
 
 module brom_p384_h_x
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			4'b0000:	bram_reg_b <= 32'h1b13ea8a;

-			4'b0001:	bram_reg_b <= 32'h8b574391;

-			4'b0010:	bram_reg_b <= 32'h8155ad27;

-			4'b0011:	bram_reg_b <= 32'h55fa1b42;

-			4'b0100:	bram_reg_b <= 32'hfb57ab8d;

-			4'b0101:	bram_reg_b <= 32'h4c117c3e;

-			4'b0110:	bram_reg_b <= 32'he8b0c8cf;

-			4'b0111:	bram_reg_b <= 32'h23c5893a;

-			4'b1000:	bram_reg_b <= 32'h19bea517;

-			4'b1001:	bram_reg_b <= 32'he29c71c2;

-			4'b1010:	bram_reg_b <= 32'h82e9f590;

-			4'b1011:	bram_reg_b <= 32'haaf06bba;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h1b13ea8a;
+       4'b0001:	bram_reg_b <= 32'h8b574391;
+       4'b0010:	bram_reg_b <= 32'h8155ad27;
+       4'b0011:	bram_reg_b <= 32'h55fa1b42;
+       4'b0100:	bram_reg_b <= 32'hfb57ab8d;
+       4'b0101:	bram_reg_b <= 32'h4c117c3e;
+       4'b0110:	bram_reg_b <= 32'he8b0c8cf;
+       4'b0111:	bram_reg_b <= 32'h23c5893a;
+       4'b1000:	bram_reg_b <= 32'h19bea517;
+       4'b1001:	bram_reg_b <= 32'he29c71c2;
+       4'b1010:	bram_reg_b <= 32'h82e9f590;
+       4'b1011:	bram_reg_b <= 32'haaf06bba;
+     endcase
 
 endmodule