1 files changed, 25 insertions, 25 deletions

diff --git a/rtl/curve/rom/brom_p384_g_y.v b/rtl/curve/rom/brom_p384_g_y.v
index c2461eb..e64d9aa 100644
--- a/rtl/curve/rom/brom_p384_g_y.v
+++ b/rtl/curve/rom/brom_p384_g_y.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_g_y
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-

+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			4'b0000:	bram_reg_b <= 32'h90ea0e5f;

-			3'b0001:	bram_reg_b <= 32'h7a431d7c;

-			4'b0010:	bram_reg_b <= 32'h1d7e819d;

-			4'b0011:	bram_reg_b <= 32'h0a60b1ce;

-			4'b0100:	bram_reg_b <= 32'hb5f0b8c0;

-			4'b0101:	bram_reg_b <= 32'he9da3113;

-			4'b0110:	bram_reg_b <= 32'h289a147c;

-			4'b0111:	bram_reg_b <= 32'hf8f41dbd;

-			4'b1000:	bram_reg_b <= 32'h9292dc29;

-			4'b1001:	bram_reg_b <= 32'h5d9e98bf;

-			4'b1010:	bram_reg_b <= 32'h96262c6f;

-			4'b1011:	bram_reg_b <= 32'h3617de4a;

-		endcase

-		
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h90ea0e5f;
+       3'b0001:	bram_reg_b <= 32'h7a431d7c;
+       4'b0010:	bram_reg_b <= 32'h1d7e819d;
+       4'b0011:	bram_reg_b <= 32'h0a60b1ce;
+       4'b0100:	bram_reg_b <= 32'hb5f0b8c0;
+       4'b0101:	bram_reg_b <= 32'he9da3113;
+       4'b0110:	bram_reg_b <= 32'h289a147c;
+       4'b0111:	bram_reg_b <= 32'hf8f41dbd;
+       4'b1000:	bram_reg_b <= 32'h9292dc29;
+       4'b1001:	bram_reg_b <= 32'h5d9e98bf;
+       4'b1010:	bram_reg_b <= 32'h96262c6f;
+       4'b1011:	bram_reg_b <= 32'h3617de4a;
+     endcase
+
 
 endmodule