1 files changed, 24 insertions, 24 deletions

diff --git a/rtl/curve/rom/brom_p384_g_x.v b/rtl/curve/rom/brom_p384_g_x.v
index 25d5103..614c7fe 100644
--- a/rtl/curve/rom/brom_p384_g_x.v
+++ b/rtl/curve/rom/brom_p384_g_x.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_g_x
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			4'b0000:	bram_reg_b <= 32'h72760ab7;

-			4'b0001:	bram_reg_b <= 32'h3a545e38;

-			4'b0010:	bram_reg_b <= 32'hbf55296c;

-			4'b0011:	bram_reg_b <= 32'h5502f25d;

-			4'b0100:	bram_reg_b <= 32'h82542a38;

-			4'b0101:	bram_reg_b <= 32'h59f741e0;

-			4'b0110:	bram_reg_b <= 32'h8ba79b98;

-			4'b0111:	bram_reg_b <= 32'h6e1d3b62;

-			4'b1000:	bram_reg_b <= 32'hf320ad74;

-			4'b1001:	bram_reg_b <= 32'h8eb1c71e;

-			4'b1010:	bram_reg_b <= 32'hbe8b0537;

-			4'b1011:	bram_reg_b <= 32'haa87ca22;

-		endcase

-		
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h72760ab7;
+       4'b0001:	bram_reg_b <= 32'h3a545e38;
+       4'b0010:	bram_reg_b <= 32'hbf55296c;
+       4'b0011:	bram_reg_b <= 32'h5502f25d;
+       4'b0100:	bram_reg_b <= 32'h82542a38;
+       4'b0101:	bram_reg_b <= 32'h59f741e0;
+       4'b0110:	bram_reg_b <= 32'h8ba79b98;
+       4'b0111:	bram_reg_b <= 32'h6e1d3b62;
+       4'b1000:	bram_reg_b <= 32'hf320ad74;
+       4'b1001:	bram_reg_b <= 32'h8eb1c71e;
+       4'b1010:	bram_reg_b <= 32'hbe8b0537;
+       4'b1011:	bram_reg_b <= 32'haa87ca22;
+     endcase
+
 
 endmodule