Promote to a repository in the core tree.

Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.

Code common between this core and the ecdsa256 core split out into a
separate library repository.

Minor cleanup (Windows-isms, indentation).

5 files changed, 0 insertions, 530 deletions

diff --git a/rtl/lowlevel/artix7/adder32_artix7.v b/rtl/lowlevel/artix7/adder32_artix7.v
deleted file mode 100644
index 5f9ba79..0000000
--- a/rtl/lowlevel/artix7/adder32_artix7.v
+++ /dev/null
@@ -1,96 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// adder32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit adder.

-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-//   this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-//   this list of conditions and the following disclaimer in the documentation
-//   and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-//   used to endorse or promote products derived from this software without
-//   specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------

-

-module adder32_artix7

-	(

-		input					clk,		// clock

-		input		[31: 0]	a,			// operand input

-		input		[31: 0]	b,			// operand input

-		output	[31: 0]	s,			// sum output

-		input					c_in,		// carry input

-		output				c_out		// carry output

-	);

-	

-		//

-		// Lower and higher parts of operand

-		//

-	wire	[17: 0]	bl = b[17: 0];

-	wire	[13: 0]	bh = b[31:18];

-

-		

-		//

-		// DSP48E1 Slice

-		//

-		

-		/* Operation Mode */

-	wire	[ 3: 0]	dsp48e1_alumode	= 4'b0000;

-	wire	[ 6: 0]	dsp48e1_opmode		= 7'b0110011;

-		

-		/* Internal Product */

-	wire	[47: 0]	p_int;

-

-	dsp48e1_wrapper dsp_adder

-	(

-		.clk			(clk),

-		

-		.ce			(1'b1),

-		

-		.carry		(c_in),

-		

-		.alumode		(dsp48e1_alumode),

-		.opmode		(dsp48e1_opmode),

-		

-		.a				({{16{1'b0}}, bh}),

-		.b				(bl),

-		.c				({{16{1'b0}}, a}),

-		

-		.p				(p_int)

-	);

-

-		//

-		// Output Mapping

-		//

-	assign s 		= p_int[31: 0];

-	assign c_out	= p_int[32];

-

-

-endmodule

-

-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------

diff --git a/rtl/lowlevel/artix7/adder47_artix7.v b/rtl/lowlevel/artix7/adder47_artix7.v
deleted file mode 100644
index 00566e4..0000000
--- a/rtl/lowlevel/artix7/adder47_artix7.v
+++ /dev/null
@@ -1,91 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// adder47_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 47-bit adder.

-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-//   this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-//   this list of conditions and the following disclaimer in the documentation
-//   and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-//   used to endorse or promote products derived from this software without
-//   specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------

-

-module adder47_artix7

-	(

-		input					clk,		// clock

-		input		[46: 0]	a,			// operand input

-		input		[46: 0]	b,			// operand input

-		output	[46: 0]	s			// sum output

-	);

-	

-		//

-		// Lower and higher parts of operand

-		//

-	wire	[17: 0]	bl = b[17: 0];

-	wire	[28: 0]	bh = b[46:18];

-

-		//

-		// DSP48E1 Slice

-		//

-		

-		/* Operation Mode */

-	wire	[ 3: 0]	dsp48e1_alumode	= 4'b0000;

-	wire	[ 6: 0]	dsp48e1_opmode		= 7'b0110011;

-		

-		/* Internal Product */

-	wire	[47: 0]	p_int;

-

-	dsp48e1_wrapper dsp_adder

-	(

-		.clk			(clk),

-		

-		.ce			(1'b1),

-		

-		.carry		(1'b0),

-		

-		.alumode		(dsp48e1_alumode),

-		.opmode		(dsp48e1_opmode),

-		

-		.a				({1'b0, bh}),

-		.b				(bl),

-		.c				({1'b0, a}),

-		

-		.p				(p_int)

-	);

-

-		//

-		// Output Mapping

-		//

-	assign s 		= p_int[46: 0];

-

-endmodule

-

-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------

diff --git a/rtl/lowlevel/artix7/dsp48e1_wrapper.v b/rtl/lowlevel/artix7/dsp48e1_wrapper.v
deleted file mode 100644
index 11a21bc..0000000
--- a/rtl/lowlevel/artix7/dsp48e1_wrapper.v
+++ /dev/null
@@ -1,159 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// dsp48e1_wrapper.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) tile wrapper.

-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-//   this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-//   this list of conditions and the following disclaimer in the documentation
-//   and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-//   used to endorse or promote products derived from this software without
-//   specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------

-

-module dsp48e1_wrapper

-	(

-		input					clk,

-		

-		input					ce,

-		

-		input		[ 6: 0]	opmode,

-		input		[ 3: 0]	alumode,

-		

-		input					carry,

-		

-		input		[29: 0]	a,

-		input		[17: 0]	b,

-		input		[47: 0]	c,

-		

-		output	[47: 0]	p

-	);

-	

-	

-		//

-		// Tile instantiation

-		//

-	DSP48E1 #
-	(
-		.AREG						(0),
-		.BREG						(0),
-		.CREG						(0),
-		.DREG						(0),
-		.MREG						(0),
-		.PREG						(1),
-		.ADREG					(0),

-		
-		.ACASCREG				(0),
-		.BCASCREG				(0),
-		.ALUMODEREG				(0),
-		.INMODEREG				(0),
-		.OPMODEREG				(0),
-		.CARRYINREG				(0),
-		.CARRYINSELREG			(0),
-
-		.A_INPUT					("DIRECT"),
-		.B_INPUT					("DIRECT"),

-		
-		.USE_DPORT				("FALSE"),
-		.USE_MULT				("DYNAMIC"),
-		.USE_SIMD				("ONE48"),
-
-		.USE_PATTERN_DETECT	("NO_PATDET"),
-		.SEL_PATTERN			("PATTERN"),
-		.SEL_MASK				("MASK"),
-		.PATTERN					(48'h000000000000),
-		.MASK						(48'h3fffffffffff),
-		.AUTORESET_PATDET		("NO_RESET")
-	)
-	DSP48E1_inst
-	(
-		.CLK					(clk),
-
-		.RSTA					(1'b0),
-		.RSTB					(1'b0),
-		.RSTC					(1'b0),
-		.RSTD					(1'b0),
-		.RSTM					(1'b0),
-		.RSTP					(1'b0),
-
-		.RSTCTRL				(1'b0),
-		.RSTINMODE			(1'b0),
-		.RSTALUMODE			(1'b0),
-		.RSTALLCARRYIN		(1'b0),
-
-		.CEA1					(1'b0),
-		.CEA2					(1'b0),
-		.CEB1					(1'b0),
-		.CEB2					(1'b0),
-		.CEC					(1'b0),
-		.CED					(1'b0),
-		.CEM					(1'b0),
-		.CEP					(ce),
-		.CEAD					(1'b0),
-		.CEALUMODE			(1'b0),
-		.CEINMODE			(1'b0),
-
-		.CECTRL				(1'b0),
-		.CECARRYIN			(1'b0),
-
-		.A						(a),
-		.B						(b),
-		.C						(c),
-		.D						({25{1'b1}}),
-		.P						(p),
-
-		.CARRYIN				(carry),
-		.CARRYOUT			(),
-		.CARRYINSEL			(3'b000),
-
-		.CARRYCASCIN		(1'b0),
-		.CARRYCASCOUT		(),
-
-		.PATTERNDETECT		(),
-		.PATTERNBDETECT	(),
-
-		.OPMODE				(opmode),
-		.ALUMODE				(alumode),
-		.INMODE				(5'b00000),
-
-		.MULTSIGNIN			(1'b0),
-		.MULTSIGNOUT		(),
-
-		.UNDERFLOW			(),
-		.OVERFLOW			(),
-
-		.ACIN					(30'd0),
-		.BCIN					(18'd0),
-		.PCIN					(48'd0),
-
-		.ACOUT				(),
-		.BCOUT				(),
-		.PCOUT				()
-  );
-

-endmodule

diff --git a/rtl/lowlevel/artix7/mac16_artix7.v b/rtl/lowlevel/artix7/mac16_artix7.v
deleted file mode 100644
index 63b74ab..0000000
--- a/rtl/lowlevel/artix7/mac16_artix7.v
+++ /dev/null
@@ -1,90 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// mac16_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 16-bit multiplier and 47-bit accumulator.

-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-//   this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-//   this list of conditions and the following disclaimer in the documentation
-//   and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-//   used to endorse or promote products derived from this software without
-//   specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------

-

-module mac16_artix7

-	(

-		input					clk,		// clock

-		input					clr,		// clear accumulator (active-high)

-		input					ce,		// enable clock (active-high)

-		input		[15: 0]	a,			// operand input

-		input		[15: 0]	b,			// operand input

-		output	[46: 0]	s			// sum output

-	);

-	

-			

-		//

-		// DSP48E1 Slice

-		//

-		

-		/* Operation Mode */

-	wire	[ 3: 0]	dsp48e1_alumode	= 4'b0000;

-	wire	[ 6: 0]	dsp48e1_opmode		= {2'b01, clr, 4'b0101};

-		

-		/* Internal Product */

-	wire	[47: 0]	p_int;

-

-	dsp48e1_wrapper dsp_adder

-	(

-		.clk			(clk),

-		

-		.ce			(ce),

-		

-		.carry		(1'b0),

-		

-		.alumode		(dsp48e1_alumode),

-		.opmode		(dsp48e1_opmode),

-		

-		.a				({{14{1'b0}}, a}),

-		.b				({{ 2{1'b0}}, b}),

-		.c				({48{1'b0}}),

-		

-		.p				(p_int)

-	);

-

-		//

-		// Output Mapping

-		//

-	assign s = p_int[46:0];

-	

-

-endmodule

-

-

-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------

diff --git a/rtl/lowlevel/artix7/subtractor32_artix7.v b/rtl/lowlevel/artix7/subtractor32_artix7.v
deleted file mode 100644
index b46ac5c..0000000
--- a/rtl/lowlevel/artix7/subtractor32_artix7.v
+++ /dev/null
@@ -1,94 +0,0 @@
-//------------------------------------------------------------------------------

-//

-// subtractor32_artix7.v

-// -----------------------------------------------------------------------------

-// Hardware (Artix-7 DSP48E1) 32-bit subtractor.

-//

-// Authors: Pavel Shatov

-//

-// Copyright (c) 2016, NORDUnet A/S

-//

-// Redistribution and use in source and binary forms, with or without

-// modification, are permitted provided that the following conditions are met:

-//

-// - Redistributions of source code must retain the above copyright notice,

-//   this list of conditions and the following disclaimer.

-//

-// - Redistributions in binary form must reproduce the above copyright notice,

-//   this list of conditions and the following disclaimer in the documentation

-//   and/or other materials provided with the distribution.

-//

-// - Neither the name of the NORDUnet nor the names of its contributors may be

-//   used to endorse or promote products derived from this software without

-//   specific prior written permission.

-//

-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-// POSSIBILITY OF SUCH DAMAGE.

-//

-//------------------------------------------------------------------------------

-

-module subtractor32_artix7

-	(

-		input					clk,

-		input		[31: 0]	a,

-		input		[31: 0]	b,

-		output	[31: 0]	d,

-		input					b_in,

-		output				b_out	

-	);

-

-		//

-		// Lower and higher parts of operand

-		//

-	wire	[17: 0]	bl = b[17: 0];

-	wire	[13: 0]	bh = b[31:18];

-	

-		//

-		// DSP48E1 Slice

-		//

-		

-		/* Operation Mode */

-	wire	[ 3: 0]	dsp48e1_alumode	= 4'b0011;

-	wire	[ 6: 0]	dsp48e1_opmode		= 7'b0110011;

-

-		/* Internal Product */	

-	wire	[47: 0]	p_int;

-	

-	dsp48e1_wrapper dsp_subtractor

-	(

-		.clk			(clk),

-	

-		.ce			(1'b1),

-		

-		.carry		(b_in),

-		

-		.alumode		(dsp48e1_alumode),

-		.opmode		(dsp48e1_opmode),

-		

-		.a				({{16{1'b0}}, bh}),

-		.b				(bl),

-		.c				({{16{1'b0}}, a}),

-		

-		.p				(p_int)

-	);

-

-		//

-		// Output Mapping

-		//

-	assign d 		= p_int[31: 0];

-	assign b_out	= p_int[32];

-

-endmodule

-

-//------------------------------------------------------------------------------

-// End-of-File

-//------------------------------------------------------------------------------