Age | Commit message (Collapse) | Author | |
---|---|---|---|
2018-04-17 | Modified the test program to verify that changes in Verilog do work.fix | Pavel V. Shatov (Meister) | |
2018-04-01 | Added more test vectors to trigger the virtually never taken path in the curve | Pavel V. Shatov (Meister) | |
point addition routine. | |||
2017-03-07 | Promote to a repository in the core tree. | Rob Austein | |
Change name of reset signal from rst_n to reset_n for consistancy with other Cryptech cores. Code common between this core and the ecdsa384 core split out into a separate library repository. Minor cleanup (Windows-isms, indentation). | |||
2017-02-12 | Various clean-ups | Pavel V. Shatov (Meister) | |
* Added sample C program for STM32 to test the core in hardware * Parametrized math modules are now instantiated with explicit operand width for clarify (previously relied on default parameter values in underlying modules) * Fixed some comments |