Promote to a repository in the core tree.

Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.

Code common between this core and the ecdsa384 core split out into a
separate library repository.

Minor cleanup (Windows-isms, indentation).

8 files changed, 156 insertions, 156 deletions

diff --git a/rtl/curve/rom/brom_p256_delta.v b/rtl/curve/rom/brom_p256_delta.v
index b9a345a..4637575 100644
--- a/rtl/curve/rom/brom_p256_delta.v
+++ b/rtl/curve/rom/brom_p256_delta.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_delta
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'h00000000;

-			3'b001:	bram_reg_b <= 32'h00000000;

-			3'b010:	bram_reg_b <= 32'h80000000;

-			3'b011:	bram_reg_b <= 32'h00000000;

-			3'b100:	bram_reg_b <= 32'h00000000;

-			3'b101:	bram_reg_b <= 32'h80000000;

-			3'b110:	bram_reg_b <= 32'h80000000;

-			3'b111:	bram_reg_b <= 32'h7fffffff;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'h00000000;
+       3'b001:	bram_reg_b <= 32'h00000000;
+       3'b010:	bram_reg_b <= 32'h80000000;
+       3'b011:	bram_reg_b <= 32'h00000000;
+       3'b100:	bram_reg_b <= 32'h00000000;
+       3'b101:	bram_reg_b <= 32'h80000000;
+       3'b110:	bram_reg_b <= 32'h80000000;
+       3'b111:	bram_reg_b <= 32'h7fffffff;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_g_x.v b/rtl/curve/rom/brom_p256_g_x.v
index 0816ef6..86aeafd 100644
--- a/rtl/curve/rom/brom_p256_g_x.v
+++ b/rtl/curve/rom/brom_p256_g_x.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_g_x
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'hd898c296;

-			3'b001:	bram_reg_b <= 32'hf4a13945;

-			3'b010:	bram_reg_b <= 32'h2deb33a0;

-			3'b011:	bram_reg_b <= 32'h77037d81;

-			3'b100:	bram_reg_b <= 32'h63a440f2;

-			3'b101:	bram_reg_b <= 32'hf8bce6e5;

-			3'b110:	bram_reg_b <= 32'he12c4247;

-			3'b111:	bram_reg_b <= 32'h6b17d1f2;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'hd898c296;
+       3'b001:	bram_reg_b <= 32'hf4a13945;
+       3'b010:	bram_reg_b <= 32'h2deb33a0;
+       3'b011:	bram_reg_b <= 32'h77037d81;
+       3'b100:	bram_reg_b <= 32'h63a440f2;
+       3'b101:	bram_reg_b <= 32'hf8bce6e5;
+       3'b110:	bram_reg_b <= 32'he12c4247;
+       3'b111:	bram_reg_b <= 32'h6b17d1f2;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_g_y.v b/rtl/curve/rom/brom_p256_g_y.v
index 4d9c61e..39f9116 100644
--- a/rtl/curve/rom/brom_p256_g_y.v
+++ b/rtl/curve/rom/brom_p256_g_y.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_g_y
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-

+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'h37bf51f5;

-			3'b001:	bram_reg_b <= 32'hcbb64068;

-			3'b010:	bram_reg_b <= 32'h6b315ece;

-			3'b011:	bram_reg_b <= 32'h2bce3357;

-			3'b100:	bram_reg_b <= 32'h7c0f9e16;

-			3'b101:	bram_reg_b <= 32'h8ee7eb4a;

-			3'b110:	bram_reg_b <= 32'hfe1a7f9b;

-			3'b111:	bram_reg_b <= 32'h4fe342e2;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'h37bf51f5;
+       3'b001:	bram_reg_b <= 32'hcbb64068;
+       3'b010:	bram_reg_b <= 32'h6b315ece;
+       3'b011:	bram_reg_b <= 32'h2bce3357;
+       3'b100:	bram_reg_b <= 32'h7c0f9e16;
+       3'b101:	bram_reg_b <= 32'h8ee7eb4a;
+       3'b110:	bram_reg_b <= 32'hfe1a7f9b;
+       3'b111:	bram_reg_b <= 32'h4fe342e2;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_h_x.v b/rtl/curve/rom/brom_p256_h_x.v
index 0b69f77..554d346 100644
--- a/rtl/curve/rom/brom_p256_h_x.v
+++ b/rtl/curve/rom/brom_p256_h_x.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_h_x
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'h4ece7ad0;

-			3'b001:	bram_reg_b <= 32'h16bd8d74;

-			3'b010:	bram_reg_b <= 32'ha42998be;

-			3'b011:	bram_reg_b <= 32'h11f904fe;

-			3'b100:	bram_reg_b <= 32'h38b77e1b;

-			3'b101:	bram_reg_b <= 32'h0e863235;

-			3'b110:	bram_reg_b <= 32'h3da77b71;

-			3'b111:	bram_reg_b <= 32'h29d05c19;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'h4ece7ad0;
+       3'b001:	bram_reg_b <= 32'h16bd8d74;
+       3'b010:	bram_reg_b <= 32'ha42998be;
+       3'b011:	bram_reg_b <= 32'h11f904fe;
+       3'b100:	bram_reg_b <= 32'h38b77e1b;
+       3'b101:	bram_reg_b <= 32'h0e863235;
+       3'b110:	bram_reg_b <= 32'h3da77b71;
+       3'b111:	bram_reg_b <= 32'h29d05c19;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_h_y.v b/rtl/curve/rom/brom_p256_h_y.v
index 362fce6..6b5b8d9 100644
--- a/rtl/curve/rom/brom_p256_h_y.v
+++ b/rtl/curve/rom/brom_p256_h_y.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_h_y
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-

+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'hc840ae07;

-			3'b001:	bram_reg_b <= 32'h3449bf97;

-			3'b010:	bram_reg_b <= 32'h94cea131;

-			3'b011:	bram_reg_b <= 32'hd431cca9;

-			3'b100:	bram_reg_b <= 32'h83f061e9;

-			3'b101:	bram_reg_b <= 32'h711814b5;

-			3'b110:	bram_reg_b <= 32'h01e58065;

-			3'b111:	bram_reg_b <= 32'hb01cbd1c;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'hc840ae07;
+       3'b001:	bram_reg_b <= 32'h3449bf97;
+       3'b010:	bram_reg_b <= 32'h94cea131;
+       3'b011:	bram_reg_b <= 32'hd431cca9;
+       3'b100:	bram_reg_b <= 32'h83f061e9;
+       3'b101:	bram_reg_b <= 32'h711814b5;
+       3'b110:	bram_reg_b <= 32'h01e58065;
+       3'b111:	bram_reg_b <= 32'hb01cbd1c;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_one.v b/rtl/curve/rom/brom_p256_one.v
index 4097874..15e3746 100644
--- a/rtl/curve/rom/brom_p256_one.v
+++ b/rtl/curve/rom/brom_p256_one.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_one
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'h00000001;

-			3'b001:	bram_reg_b <= 32'h00000000;

-			3'b010:	bram_reg_b <= 32'h00000000;

-			3'b011:	bram_reg_b <= 32'h00000000;

-			3'b100:	bram_reg_b <= 32'h00000000;

-			3'b101:	bram_reg_b <= 32'h00000000;

-			3'b110:	bram_reg_b <= 32'h00000000;

-			3'b111:	bram_reg_b <= 32'h00000000;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'h00000001;
+       3'b001:	bram_reg_b <= 32'h00000000;
+       3'b010:	bram_reg_b <= 32'h00000000;
+       3'b011:	bram_reg_b <= 32'h00000000;
+       3'b100:	bram_reg_b <= 32'h00000000;
+       3'b101:	bram_reg_b <= 32'h00000000;
+       3'b110:	bram_reg_b <= 32'h00000000;
+       3'b111:	bram_reg_b <= 32'h00000000;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_q.v b/rtl/curve/rom/brom_p256_q.v
index fe94593..101a524 100644
--- a/rtl/curve/rom/brom_p256_q.v
+++ b/rtl/curve/rom/brom_p256_q.v
@@ -33,36 +33,36 @@
 `timescale 1ns / 1ps
 
 module brom_p256_q
-   (
-		input		wire				clk,
-		input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 3-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-

+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//

-		case (b_addr)

-			3'b000:	bram_reg_b <= 32'hffffffff;

-			3'b001:	bram_reg_b <= 32'hffffffff;

-			3'b010:	bram_reg_b <= 32'hffffffff;

-			3'b011:	bram_reg_b <= 32'h00000000;

-			3'b100:	bram_reg_b <= 32'h00000000;

-			3'b101:	bram_reg_b <= 32'h00000000;

-			3'b110:	bram_reg_b <= 32'h00000001;

-			3'b111:	bram_reg_b <= 32'hffffffff;

-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       3'b000:	bram_reg_b <= 32'hffffffff;
+       3'b001:	bram_reg_b <= 32'hffffffff;
+       3'b010:	bram_reg_b <= 32'hffffffff;
+       3'b011:	bram_reg_b <= 32'h00000000;
+       3'b100:	bram_reg_b <= 32'h00000000;
+       3'b101:	bram_reg_b <= 32'h00000000;
+       3'b110:	bram_reg_b <= 32'h00000001;
+       3'b111:	bram_reg_b <= 32'hffffffff;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p256_zero.v b/rtl/curve/rom/brom_p256_zero.v
index f6d19a1..2672cf2 100644
--- a/rtl/curve/rom/brom_p256_zero.v
+++ b/rtl/curve/rom/brom_p256_zero.v
@@ -33,14 +33,14 @@
 `timescale 1ns / 1ps
 
 module brom_p256_zero
-   (
-		//input		wire				clk,
-		//input		wire	[ 3-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   //input		wire			clk,
+   //input		wire	[ 3-1:0]	b_addr,
+   output wire [32-1:0] b_out
+   );
 
-

-	assign b_out = {32{1'b0}};

+
+   assign b_out = {32{1'b0}};
 
    //
    // Output Registers
@@ -52,19 +52,19 @@ module brom_p256_zero
 
    //
    // Read-Only Port B
-	//
-	//always @(posedge clk)
-		//

-		//case (b_addr)

-			//3'b000:	bram_reg_b <= 32'h00000000;

-			//3'b001:	bram_reg_b <= 32'h00000000;

-			//3'b010:	bram_reg_b <= 32'h00000000;

-			//3'b011:	bram_reg_b <= 32'h00000000;

-			//3'b100:	bram_reg_b <= 32'h00000000;

-			//3'b101:	bram_reg_b <= 32'h00000000;

-			//3'b110:	bram_reg_b <= 32'h00000000;

-			//3'b111:	bram_reg_b <= 32'h00000000;

-		//endcase
+   //
+   //always @(posedge clk)
+   //
+   //case (b_addr)
+   //3'b000:	bram_reg_b <= 32'h00000000;
+   //3'b001:	bram_reg_b <= 32'h00000000;
+   //3'b010:	bram_reg_b <= 32'h00000000;
+   //3'b011:	bram_reg_b <= 32'h00000000;
+   //3'b100:	bram_reg_b <= 32'h00000000;
+   //3'b101:	bram_reg_b <= 32'h00000000;
+   //3'b110:	bram_reg_b <= 32'h00000000;
+   //3'b111:	bram_reg_b <= 32'h00000000;
+   //endcase
 
 
 endmodule