//======================================================================
//
// Copyright (c) 2016, NORDUnet A/S All rights reserved.
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//======================================================================
`timescale 1ns / 1ps
module brom_p256_q
(
input wire clk,
input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'hffffffff;
3'b001: bram_reg_b <= 32'hffffffff;
3'b010: bram_reg_b <= 32'hffffffff;
3'b011: bram_reg_b <= 32'h00000000;
3'b100: bram_reg_b <= 32'h00000000;
3'b101: bram_reg_b <= 32'h00000000;
3'b110: bram_reg_b <= 32'h00000001;
3'b111: bram_reg_b <= 32'hffffffff;
endcase
endmodule
