diff options
Diffstat (limited to 'src/rtl/ipcore/multiplier_s6.v')
-rw-r--r-- | src/rtl/ipcore/multiplier_s6.v | 80 |
1 files changed, 1 insertions, 79 deletions
diff --git a/src/rtl/ipcore/multiplier_s6.v b/src/rtl/ipcore/multiplier_s6.v index 7a7cb5e..f194325 100644 --- a/src/rtl/ipcore/multiplier_s6.v +++ b/src/rtl/ipcore/multiplier_s6.v @@ -35,14 +35,12 @@ module multiplier_s6 ( clk, a, b, p -)/* synthesis syn_black_box syn_noprune=1 */; +); input clk; input [31 : 0] a; input [31 : 0] b; output [63 : 0] p; - // synthesis translate_off - wire \blk00000001/sig000001c7 ; wire \blk00000001/sig000001c6 ; wire \blk00000001/sig000001c5 ; @@ -1406,80 +1404,4 @@ p[49], p[48], p[47], p[46], p[45], p[44], p[43], p[42], p[41], p[40], p[39], p[3 .P(\blk00000001/sig000000b2 ) ); -// synthesis translate_on - endmodule - -// synthesis translate_off - -`ifndef GLBL -`define GLBL - -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (weak1, weak0) GSR = GSR_int; - assign (weak1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule - -`endif - -// synthesis translate_on |