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| author | Paul Selkirk <paul@psgd.org> | 2015-07-17 11:57:51 -0400 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-07-17 11:57:51 -0400 |
| commit | 1acddf19bb8c39f5202d80af068b5ffd14797f4b (patch) | |
| tree | 5369e18a361f4e88b4c0f751fe5f202e566d31f3 /src/rtl/ipcore/coregen.cgp | |
Initial commit
Diffstat (limited to 'src/rtl/ipcore/coregen.cgp')
| -rw-r--r-- | src/rtl/ipcore/coregen.cgp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/rtl/ipcore/coregen.cgp b/src/rtl/ipcore/coregen.cgp new file mode 100644 index 0000000..8bc2e70 --- /dev/null +++ b/src/rtl/ipcore/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = csg324 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false |