diff options
author | Paul Selkirk <paul@psgd.org> | 2015-07-17 11:57:51 -0400 |
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committer | Paul Selkirk <paul@psgd.org> | 2015-07-17 11:57:51 -0400 |
commit | 1acddf19bb8c39f5202d80af068b5ffd14797f4b (patch) | |
tree | 5369e18a361f4e88b4c0f751fe5f202e566d31f3 /src/rtl/ipcore/_xmsgs/cg.xmsgs |
Initial commit
Diffstat (limited to 'src/rtl/ipcore/_xmsgs/cg.xmsgs')
-rw-r--r-- | src/rtl/ipcore/_xmsgs/cg.xmsgs | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/rtl/ipcore/_xmsgs/cg.xmsgs b/src/rtl/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..f165d5f --- /dev/null +++ b/src/rtl/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,39 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'multiplier_s6'...</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
|