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//======================================================================
//
// Copyright: 2019, The Commons Conservancy Cryptech Project
// SPDX-License-Identifier: BSD-3-Clause
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module modexpng_dsp_slice_mult_wrapper_xilinx #
(
AB_INPUT = "DIRECT",
B_REG = 2
)
(
clk,
ce_a1, ce_b1, ce_a2, ce_b2,
ce_m, ce_p, ce_mode,
a, b, p,
inmode, opmode, alumode,
casc_a_in, casc_b_in,
casc_a_out, casc_b_out
);
`include "modexpng_parameters.vh"
`include "modexpng_dsp48e1.vh"
input clk;
input ce_a1;
input ce_b1;
input ce_a2;
input ce_b2;
input ce_m;
input ce_p;
input ce_mode;
input [ WORD_EXT_W -1:0] a;
input [ WORD_W -1:0] b;
output [ MAC_W -1:0] p;
input [ DSP48E1_INMODE_W -1:0] inmode;
input [ DSP48E1_OPMODE_W -1:0] opmode;
input [DSP48E1_ALUMODE_W -1:0] alumode;
input [ DSP48E1_A_W -1:0] casc_a_in;
input [ DSP48E1_B_W -1:0] casc_b_in;
output [ DSP48E1_A_W -1:0] casc_a_out;
output [ DSP48E1_B_W -1:0] casc_b_out;
wire [DSP48E1_P_W - MAC_W -1:0] p_dummy;
DSP48E1 #
(
.AREG (2),
.BREG (B_REG),
.CREG (0),
.DREG (0),
.ADREG (0),
.MREG (1),
.PREG (1),
.ACASCREG (1),
.BCASCREG (1),
.INMODEREG (0),
.OPMODEREG (1),
.ALUMODEREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.A_INPUT (AB_INPUT),
.B_INPUT (AB_INPUT),
.USE_DPORT ("FALSE"),
.USE_MULT ("DYNAMIC"),
.USE_SIMD ("ONE48"),
.MASK ({DSP48E1_P_W{1'b1}}),
.PATTERN ({DSP48E1_P_W{1'b0}}),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.AUTORESET_PATDET ("NO_RESET")
)
DSP48E1_inst
(
.CLK (clk),
.CEA1 (ce_a1),
.CEB1 (ce_b1),
.CEA2 (ce_a2),
.CEB2 (ce_b2),
.CEAD (1'b0),
.CEC (1'b0),
.CED (1'b0),
.CEM (ce_m),
.CEP (ce_p),
.CEINMODE (1'b0),
.CECTRL (ce_mode),
.CEALUMODE (1'b0),
.CECARRYIN (1'b0),
.A ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
.B ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
.C ({DSP48E1_C_W{1'b0}}),
.D ({DSP48E1_D_W{1'b0}}),
.P ({p_dummy, p}),
.INMODE (inmode),
.OPMODE (opmode),
.ALUMODE (alumode),
.ACIN (casc_a_in),
.BCIN (casc_b_in),
.ACOUT (casc_a_out),
.BCOUT (casc_b_out),
.PCIN ({DSP48E1_P_W{1'b0}}),
.PCOUT (),
.CARRYCASCIN (1'b0),
.CARRYCASCOUT (),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTD (1'b0),
.RSTM (1'b0),
.RSTP (1'b0),
.RSTINMODE (1'b0),
.RSTCTRL (1'b0),
.RSTALUMODE (1'b0),
.RSTALLCARRYIN (1'b0),
.UNDERFLOW (),
.OVERFLOW (),
.PATTERNDETECT (),
.PATTERNBDETECT (),
.CARRYIN (1'b0),
.CARRYOUT (),
.CARRYINSEL (3'b000),
.MULTSIGNIN (1'b0),
.MULTSIGNOUT ()
);
endmodule
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