| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-01 | Moved to "modexpng_fpga_model" repo, this one was meant for Verilog. | Pavel V. Shatov (Meister) | |
| 2019-04-04 | Fixed 4096-bit test vector generation. | Pavel V. Shatov (Meister) | |
| 2019-03-23 | Updated readme file. | Pavel V. Shatov (Meister) | |
| 2019-03-23 | Added blinding support to test vector generation scripts. | Pavel V. Shatov (Meister) | |
| 2019-03-23 | Instructions on how to use the vector generation scripts. | Pavel V. Shatov (Meister) | |
| 2019-03-23 | Don't track the test vector itself. | Pavel V. Shatov (Meister) | |
| 2019-03-23 | Randomized test vector generation scripts for ModExpNG. | Pavel V. Shatov (Meister) | |
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index : core/math/modexpng | |
| "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA | git repositories |
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