| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-10-03 | Reworked storage architecture (moved I/O memory to a separate module, since ↵ | Pavel V. Shatov (Meister) | |
| there's only one instance of input/output values, while storage manager has dual storage space for P and Q multipliers). Started working on microcoded layer, added input operation and modular multiplication. | |||
| 2019-10-03 | Redesigned storage modules, added top-level module, added I/O storage space. | Pavel V. Shatov (Meister) | |
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) | |
| have eight 4kbit entries and occupy one 36K BRAM tile. | |||
| 2019-10-01 | Major rewrite (different core hierarchy, buses, wrappers, etc). | Pavel V. Shatov (Meister) | |
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index : core/math/modexpng | |
| "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA | git repositories |
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