Reworked storage architecture (moved I/O memory to a separate module, since there's

only one instance of input/output values, while storage manager has dual storage space
for P and Q multipliers).

Started working on microcoded layer, added input operation and modular multiplication.

1 files changed, 7 insertions, 132 deletions

diff --git a/rtl/modexpng_storage_block.v b/rtl/modexpng_storage_block.v
index d5b9b24..f1d5ae2 100644
--- a/rtl/modexpng_storage_block.v
+++ b/rtl/modexpng_storage_block.v
@@ -29,26 +29,7 @@ module modexpng_storage_block
     rd_narrow_xy_bank,
     rd_narrow_xy_addr,
     rd_narrow_x_dout,
-    rd_narrow_y_dout,
-    
-    bus_cs,
-    bus_we,
-    bus_addr,
-    bus_data_wr,
-    bus_data_rd,
-    
-    in_1_en,
-    in_1_addr,
-    in_1_dout,
-    
-    in_2_en,
-    in_2_addr,
-    in_2_dout,
-    
-    out_en,
-    out_we,
-    out_addr,
-    out_din
+    rd_narrow_y_dout
 );
 
     //
@@ -93,25 +74,6 @@ module modexpng_storage_block
     output [                  WORD_EXT_W    -1:0] rd_narrow_x_dout;
     output [                  WORD_EXT_W    -1:0] rd_narrow_y_dout;
 
-    input                                         bus_cs;
-    input                                         bus_we;
-    input  [2 + BANK_ADDR_W + BUS_OP_ADDR_W -1:0] bus_addr;
-    input  [                  BUS_DATA_W    -1:0] bus_data_wr;
-    output [                  BUS_DATA_W    -1:0] bus_data_rd;
-    
-    input                                         in_1_en;
-    input  [    BANK_ADDR_W + OP_ADDR_W     -1:0] in_1_addr;
-    output [                  WORD_W        -1:0] in_1_dout;
-    
-    input                                         in_2_en;
-    input  [    BANK_ADDR_W + OP_ADDR_W     -1:0] in_2_addr;
-    output [                  WORD_W        -1:0] in_2_dout;
-    
-    input                                         out_en;
-    input                                         out_we;
-    input  [    BANK_ADDR_W + OP_ADDR_W     -1:0] out_addr;
-    input  [                  WORD_W        -1:0] out_din;
-
     
     //
     // Internal Registers
@@ -119,8 +81,6 @@ module modexpng_storage_block
     reg rd_wide_xy_reg_ena     = 1'b0;
     reg rd_wide_xy_reg_ena_aux = 1'b0;
     reg rd_narrow_xy_reg_ena   = 1'b0;
-    reg in_1_reg_en            = 1'b0;
-    reg in_2_reg_en            = 1'b0;
 
     always @(posedge clk)
         //
@@ -128,14 +88,10 @@ module modexpng_storage_block
             rd_wide_xy_reg_ena     <= 1'b0;
             rd_wide_xy_reg_ena_aux <= 1'b0;
             rd_narrow_xy_reg_ena   <= 1'b0;
-            in_1_reg_en            <= 1'b0;
-            in_2_reg_en            <= 1'b0;
         end else begin
             rd_wide_xy_reg_ena     <= rd_wide_xy_ena;
             rd_wide_xy_reg_ena_aux <= rd_wide_xy_ena_aux;
             rd_narrow_xy_reg_ena   <= rd_narrow_xy_ena;
-            in_1_reg_en            <= in_1_en;
-            in_2_reg_en            <= in_2_en;
         end
     
     //
@@ -161,7 +117,7 @@ module modexpng_storage_block
             //
             assign rd_wide_xy_offset[z] = {1'b0, rd_wide_xy_bank, rd_wide_xy_addr[z*OP_ADDR_W +: OP_ADDR_W]};
             //
-            modexpng_sdp_36k_wrapper wide_bram_x
+            modexpng_sdp_36k_x18_wrapper wide_bram_x
             (
                 .clk    (clk),
                 
@@ -176,7 +132,7 @@ module modexpng_storage_block
                 .doutb  (rd_wide_x_dout[z*WORD_EXT_W +: WORD_EXT_W])
             );
             //
-            modexpng_sdp_36k_wrapper wide_bram_y
+            modexpng_sdp_36k_x18_wrapper wide_bram_y
             (
                 .clk    (clk),
 
@@ -197,7 +153,7 @@ module modexpng_storage_block
     //
     // Auxilary Storage
     //
-    modexpng_sdp_36k_wrapper wide_bram_x_aux
+    modexpng_sdp_36k_x18_wrapper wide_bram_x_aux
     (
         .clk    (clk),
 
@@ -212,7 +168,7 @@ module modexpng_storage_block
         .doutb  (rd_wide_x_dout_aux)
     );
     //
-    modexpng_sdp_36k_wrapper wide_bram_y_aux
+    modexpng_sdp_36k_x18_wrapper wide_bram_y_aux
     (
         .clk    (clk),
 
@@ -230,7 +186,7 @@ module modexpng_storage_block
     //
     // "Narrow" Storage
     //
-    modexpng_sdp_36k_wrapper narrow_bram_x
+    modexpng_sdp_36k_x18_wrapper narrow_bram_x
     (
         .clk    (clk),
 
@@ -245,7 +201,7 @@ module modexpng_storage_block
         .doutb  (rd_narrow_x_dout)
     );
 
-    modexpng_sdp_36k_wrapper narrow_bram_y
+    modexpng_sdp_36k_x18_wrapper narrow_bram_y
     (
         .clk    (clk),
 
@@ -260,87 +216,6 @@ module modexpng_storage_block
         .doutb  (rd_narrow_y_dout)
     );
 
-    //
-    // INPUT, OUTPUT Storage Buffers
-    //
-    wire [                          2 -1:0] bus_addr_msb = bus_addr[BANK_ADDR_W + BUS_OP_ADDR_W +: 2];
-    wire [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] bus_addr_lsb = bus_addr[BANK_ADDR_W + BUS_OP_ADDR_W -1:0];
-    reg  [                          2 -1:0] bus_addr_msb_dly;
-    wire [              BUS_DATA_W    -1:0] bus_data_rd_input_1;
-    wire [              BUS_DATA_W    -1:0] bus_data_rd_output;
-
-    wire                                    bus_data_wr_input_1 = bus_data_wr && (bus_addr_msb == 2'd0);
-    wire                                    bus_data_wr_input_2 = bus_data_wr && (bus_addr_msb == 2'd1);
-
-    /* INPUT_1 */
-    modexpng_sdp_36k_x16_x32_wrapper bram_input_1
-    (
-        .clk        (clk),                  // core clock
-        .clk_bus    (clk_bus),              // bus clock
-    
-        .ena        (bus_cs),               // bus side read-write
-        .wea        (bus_data_wr_input_1),  //
-        .addra      (bus_addr_lsb),         //
-        .dina       (bus_data_wr),          //
-        .douta      (bus_data_rd_input_1),  //
-    
-        .enb        (in_1_en),              // core side read-only
-        .regceb     (in_1_reg_en),          //
-        .addrb      (in_1_addr),            //
-        .doutb      (in_1_dout)             //
-    );
-    
-    
-    /* INPUT_2 */
-    modexpng_sdp_36k_x16_x32_wrapper bram_input_2
-    (
-        .clk        (clk),                  // core clock
-        .clk_bus    (clk_bus),              // bus clock
-    
-        .ena        (bus_cs),               // bus side write-only
-        .wea        (bus_data_wr_input_2),  //
-        .addra      (bus_addr_lsb),         //
-        .dina       (bus_data_wr),          //
-    
-        .enb        (in_2_en),              // core side read-only
-        .regceb     (in_2_reg_en),          //
-        .addrb      (in_2_addr),            //
-        .doutb      (in_2_dout)             //
-    );
-
-
-    /* OUTPUT */
-    modexpng_sdp_36k_x32_x16_wrapper bram_output
-    (
-        .clk        (clk),                  // core clock 
-        .clk_bus    (clk_bus),              // bus clock
-    
-        .ena        (out_en),               // core side write-only
-        .wea        (out_we),               //
-        .addra      (out_addr),             //
-        .dina       (out_din),              //
-    
-        .enb        (bus_cs),               // bus side read-only
-        .addrb      (bus_addr_lsb),         //
-        .doutb      (bus_data_rd_output)    //
-    );
-
-    reg [31: 0] bus_data_rd_mux;
-    assign bus_data_rd = bus_data_rd_mux;
-
-    always @(posedge clk_bus)
-        bus_addr_msb_dly <= bus_addr_msb;
-
-    always @(*)
-        //
-        case (bus_addr_msb_dly)
-            //
-            2'd0: bus_data_rd_mux = bus_data_rd_input_1;
-            2'd1: bus_data_rd_mux = 32'hDEADC0DE;
-            2'd2: bus_data_rd_mux = bus_data_rd_output;
-            2'd3: bus_data_rd_mux = 32'hDEADC0DE;
-            //
-        endcase
 
 endmodule