Age | Commit message (Collapse) | Author | |
---|---|---|---|
2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) | |
2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) | |
faster than the bus clock now. It can be the same, or say four times faster. | |||
2019-10-21 | Entire CRT signature algorithm works by now. | Pavel V. Shatov (Meister) | |
Moved micro-operations handler into a separate module file, this way we don't have any synthesized stuff in the top-level module, just instantiations. This is more consistent from the design partitioning point of view. Btw, Xilinx claims their tools work better that way too, but who knows... Added optional simulation-only code to assist debugging. Un-comment the ENABLE_DEBUG `define in 'rtl/modexpng_parameters.vh' to use, but don't ever try to synthesize the core with debugging enabled. |