core/math/modexpng - "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA

Age	Commit message (Expand)	Author
2020-01-30	Accomodate the changes to DSP slice wrappers.	Pavel V. Shatov (Meister)
2020-01-21	Tiny cosmetic typo fix ("dst" -> "dsp")	Pavel V. Shatov (Meister)
2020-01-16	This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slices	Pavel V. Shatov (Meister)
2020-01-16	Reworked modular subtraction micro-operation. Previously it used "two-pass"	Pavel V. Shatov (Meister)
2020-01-16	Turns out, fabric addition and subtraction in the general worker module are	Pavel V. Shatov (Meister)
2020-01-16	Had to rework the general worker module to reach 180 MHz core clock. The module	Pavel V. Shatov (Meister)
2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)
2019-10-21	Further work:	Pavel V. Shatov (Meister)
2019-10-21	Added support for non-CRT mode. Further refactoring.	Pavel V. Shatov (Meister)
2019-10-21	Added the regular (not modular) addition operation required during the final	Pavel V. Shatov (Meister)
2019-10-21	Added "MERGE_LH" micro-operation. To be able to do Garner's formula we need	Pavel V. Shatov (Meister)
2019-10-21	Refactored general worker module	Pavel V. Shatov (Meister)
2019-10-03	Added more micro-operations, entire Montgomery exponentiation ladder works now.	Pavel V. Shatov (Meister)
2019-10-03	Added more micro-operations, also added "general worker" module. The worker i...	Pavel V. Shatov (Meister)