core/math/modexpng - "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA

Age	Commit message (Collapse)	Author
2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)

2019-10-21	Reworked testbench, clk_sys and clk_core can now have any ratio, not	Pavel V. Shatov (Meister)
	necessarily 1:2. Fixed compile-time issue where ISE fails to place two DSP slices next to each other, if A and/or B cascade path(s) between then are partially connected. Basically, if cascade is used, entire bus must be connected.
2019-10-21	Redesigned the testbench. Core clock does not necessarily need to be twice	Pavel V. Shatov (Meister)
	faster than the bus clock now. It can be the same, or say four times faster.