core/math/modexpng - "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA

Age	Commit message (Collapse)	Author
2019-10-21	Redesigned the testbench. Core clock does not necessarily need to be twice	Pavel V. Shatov (Meister)
	faster than the bus clock now. It can be the same, or say four times faster.
2019-10-03	Added more micro-operations, also added "general worker" module. The worker ↵	Pavel V. Shatov (Meister)
	is basically a block memory data mover, but it can also do some supporting operations required for the Garner's formula part of the exponentiation.
2019-10-01	Redesigned core architecture, unified bank structure. All storage blocks now	Pavel V. Shatov (Meister)
	have eight 4kbit entries and occupy one 36K BRAM tile.
2019-10-01	Major rewrite (different core hierarchy, buses, wrappers, etc).	Pavel V. Shatov (Meister)