core/math/modexpng - "Next-generation" modular exponentiation using specialized DSP slices present in Artix-7 FPGA

Age	Commit message (Expand)	Author
2020-02-03	Improved debugging options:	Pavel V. Shatov (Meister)
2020-02-03	Adapted to the changes in the DSP slice wrappers.	Pavel V. Shatov (Meister)
2020-02-03	Added new DSP slice OPMODEs for the new recombination algorithm.	Pavel V. Shatov (Meister)
2020-02-03	Updated DSP slice wrappers for the new partial product recombination algorithm:	Pavel V. Shatov (Meister)
2020-02-03	Better handling of debug output (no need to manally adjust word count anymore).	Pavel V. Shatov (Meister)
2020-01-30	Uniform testbenches.	Pavel V. Shatov (Meister)
2020-01-30	This commit accomodates the changes made to DSP slice wrappers and also fixes	Pavel V. Shatov (Meister)
2020-01-30	Accomodate the changes to DSP slice wrappers.	Pavel V. Shatov (Meister)
2020-01-30	* more consistent port names	Pavel V. Shatov (Meister)
2020-01-30	Cosmetic rename of FSM states.	Pavel V. Shatov (Meister)
2020-01-21	Bump version number.	Pavel V. Shatov (Meister)
2020-01-21	Cosmetic change to easily switch tests on/off.	Pavel V. Shatov (Meister)
2020-01-21	Refactored the MMM module, now uses meaningful constant names from the include	Pavel V. Shatov (Meister)
2020-01-21	Refactored MMM recombinator module, accomodated the changes in DSP slice	Pavel V. Shatov (Meister)
2020-01-21	Update DSP wrapper instance names.	Pavel V. Shatov (Meister)
2020-01-21	The I/O manager has to work in sync with the general worker module. Made the	Pavel V. Shatov (Meister)
2020-01-21	Renumbered micro-operations.	Pavel V. Shatov (Meister)
2020-01-21	Refactored modular reductor module.	Pavel V. Shatov (Meister)
2020-01-21	Added more meaningful constants to avoid certain hardcoded numbers.	Pavel V. Shatov (Meister)
2020-01-21	Tiny cosmetic typo fix ("dst" -> "dsp")	Pavel V. Shatov (Meister)
2020-01-20	For the new general worker module to work we need dynamic switching of DSP	Pavel V. Shatov (Meister)
2020-01-20	Updated uOP engine to match the changes made to the general worker module	Pavel V. Shatov (Meister)
2020-01-20	Updated microcode source to match the changes made to general worker module.	Pavel V. Shatov (Meister)
2020-01-20	Cosmetic fix that only involves debug output during simulation.	Pavel V. Shatov (Meister)
2020-01-20	Added two pairs of new wrappers.	Pavel V. Shatov (Meister)
2020-01-20	Removed old DSP wrappers.	Pavel V. Shatov (Meister)
2020-01-20	* DSP slices now have two use modes: MULT and ADD/SUB	Pavel V. Shatov (Meister)
2020-01-16	This commit modifies the REGULAR_ADD_UNEVEN micro-operation to use DSP slices	Pavel V. Shatov (Meister)
2020-01-16	Reworked modular subtraction micro-operation. Previously it used "two-pass"	Pavel V. Shatov (Meister)
2020-01-16	Turns out, fabric addition and subtraction in the general worker module are	Pavel V. Shatov (Meister)
2020-01-16	Had to rework the general worker module to reach 180 MHz core clock. The module	Pavel V. Shatov (Meister)
2019-11-26	One more cosmetic fix.	Pavel V. Shatov (Meister)
2019-11-26	Cosmetic fix.	Pavel V. Shatov (Meister)
2019-11-26	Forgot to push minor cosmetic fix.	Pavel V. Shatov (Meister)
2019-11-20	Small change to the reductor module to try to get past 180 MHz. Previously BRAM	Pavel V. Shatov (Meister)
2019-11-19	Removed the latch accidentally created while pipelining the uOP engine module.	Pavel V. Shatov (Meister)
2019-11-18	Refactored reductor module.	Pavel V. Shatov (Meister)
2019-11-16	The uOP engine didn't compile at 180 MHz. The pipeline had two stages: FETCH	Pavel V. Shatov (Meister)
2019-11-13	Beautified the README.md, should look somewhat less nasty now.	Pavel V. Shatov (Meister)
2019-10-23	Added missing copyright headers.	Pavel V. Shatov (Meister)
2019-10-23	Added demo driver code for STM32.	Pavel V. Shatov (Meister)
2019-10-23	Added readme file.	Pavel V. Shatov (Meister)
2019-10-23	Fixed port width mismatch warning.	Pavel V. Shatov (Meister)
2019-10-23	Added simulation-only code to measure multiplier load.	Pavel V. Shatov (Meister)
2019-10-23	Fixed all the testbenches to work with the latest RTL sources.	Pavel V. Shatov (Meister)
2019-10-21	Reworked testbench, clk_sys and clk_core can now have any ratio, not	Pavel V. Shatov (Meister)
2019-10-21	Further work:	Pavel V. Shatov (Meister)
2019-10-21	Added support for non-CRT mode. Further refactoring.	Pavel V. Shatov (Meister)
2019-10-21	Redesigned the testbench. Core clock does not necessarily need to be twice	Pavel V. Shatov (Meister)
2019-10-21	Entire CRT signature algorithm works by now.	Pavel V. Shatov (Meister)