diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-30 20:06:34 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-01-30 20:06:34 +0300 |
| commit | 9217682c475a05c9072abf22faeeba1987edf7b5 (patch) | |
| tree | 52ce766242ff804213d8bfa901e0f810d5df0fb3 | |
| parent | d2ae99a4f3728ec9fe8f07632a39f07f905cef58 (diff) | |
Uniform testbenches.
| -rw-r--r-- | bench/tb_core_full_1024.v | 6 | ||||
| -rw-r--r-- | bench/tb_core_full_512.v | 34 |
2 files changed, 30 insertions, 10 deletions
diff --git a/bench/tb_core_full_1024.v b/bench/tb_core_full_1024.v index 96d918e..48a742a 100644 --- a/bench/tb_core_full_1024.v +++ b/bench/tb_core_full_1024.v @@ -331,7 +331,7 @@ module tb_core_full_1024; sync_clk_bus; // switch to slow bus clock core_set_input; // write to core input banks - + /**//**/ sync_clk; // switch to fast core clock core_set_crt_mode(1); // enable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -341,7 +341,7 @@ module tb_core_full_1024; core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values core_print_load; // - + /**//**/ sync_clk; // switch to fast core clock core_set_crt_mode(0); // disable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -351,6 +351,7 @@ module tb_core_full_1024; core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values core_print_load; // + /**//**/ end endtask @@ -519,7 +520,6 @@ module tb_core_full_1024; endtask - // // _bus_drive() // diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v index f17b56c..464be0a 100644 --- a/bench/tb_core_full_512.v +++ b/bench/tb_core_full_512.v @@ -273,7 +273,7 @@ module tb_core_full_512; sync_clk_bus; // switch to slow bus clock core_set_input; // write to core input banks - /*//*/ + /**//**/ sync_clk; // switch to fast core clock core_set_crt_mode(1); // enable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -282,7 +282,8 @@ module tb_core_full_512; sync_clk_bus; // switch to slow bus clock core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values - /*//*/ + core_print_load; // + /**//**/ sync_clk; // switch to fast core clock core_set_crt_mode(0); // disable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -291,7 +292,8 @@ module tb_core_full_512; sync_clk_bus; // switch to slow bus clock core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values - /*//*/ + core_print_load; // + /**//**/ end endtask @@ -566,12 +568,30 @@ module tb_core_full_512; // // Multiplier Load Calculator // - integer cyc_total = 0; - + real load_cyc_total_prev = 0.0; + real load_cyc_mult_prev = 0.0; + + real load_cyc_total = 0.0; + always @(posedge clk) // if (!core_valid) - cyc_total <= cyc_total + 1'b1; - + load_cyc_total <= load_cyc_total + 1.0; + + task core_print_load; + real delta_cyc_total, delta_cyc_mult, load_pct; + begin + `ifndef MODEXPNG_ENABLE_DEBUG + $display("core_print_load: Multiplier load was not calculated, since MODEXPNG_ENABLE_DEBUG was no defined."); + `else + delta_cyc_total = load_cyc_total - load_cyc_total_prev; + delta_cyc_mult = uut.mmm_x.load_cyc_mult - load_cyc_mult_prev; + load_pct = 100.0 * delta_cyc_mult / delta_cyc_total; + $display("Multiplier load: %.1f%%", load_pct); + load_cyc_total_prev = load_cyc_total; + load_cyc_mult_prev = uut.mmm_x.load_cyc_mult; + `endif + end + endtask endmodule |