1 files changed, 67 insertions, 0 deletions
diff --git a/rtl/modexpng_sdp_36k_x18_wrapper_generic.v b/rtl/modexpng_sdp_36k_x18_wrapper_generic.v
new file mode 100644
index 0000000..84c8e09
--- /dev/null
+++ b/rtl/modexpng_sdp_36k_x18_wrapper_generic.v
@@ -0,0 +1,67 @@
+module modexpng_sdp_36k_x18_wrapper_generic
+(
+    clk,
+    
+    ena, wea,
+    addra, dina,
+    
+    enb, regceb,
+    addrb, doutb
+);
+
+
+    //
+    // Headers
+    //
+    `include "modexpng_parameters.vh"
+
+
+    //
+    // Ports
+    //
+    input                                 clk;
+    
+    input                                 ena;
+    input                                 wea;
+    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addra;
+    input  [             WORD_EXT_W -1:0] dina;
+    
+    input                                 enb;
+    input                                 regceb;
+    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addrb;
+    output [             WORD_EXT_W -1:0] doutb;
+
+    //
+    // Memory
+    //
+    reg [WORD_EXT_W -1:0] mem[0:2**(BANK_ADDR_W+OP_ADDR_W)-1];
+   
+    //
+    // Write Port
+    //
+    always @(posedge clk)
+        //
+        if (ena && wea)
+            mem[addra] <= dina;
+            
+    //
+    // Read Port
+    //
+    reg [WORD_EXT_W -1:0] doutb_reg1;
+    reg [WORD_EXT_W -1:0] doutb_reg2;
+    
+    assign doutb = doutb_reg2;
+    
+    always @(posedge clk)
+        //
+        if (enb)
+            doutb_reg1 <= mem[addrb];
+            
+    always @(posedge clk)
+        //
+        if (regceb)
+            doutb_reg2 <= doutb_reg1;
+    
+
+
+endmodule