diff options
Diffstat (limited to 'rtl/modexpng_dsp_array_block.v')
| -rw-r--r-- | rtl/modexpng_dsp_array_block.v | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v new file mode 100644 index 0000000..9c4ee93 --- /dev/null +++ b/rtl/modexpng_dsp_array_block.v @@ -0,0 +1,143 @@ +module modexpng_dsp_array_block +( + input clk, + + input ce_a, + input ce_b, + input ce_m, + input ce_p, + input ce_mode, + + input [9 -1:0] mode_z, + + input [5*18-1:0] a, + input [1*16-1:0] b, + output [9*47-1:0] p +); + + `include "modexpng_parameters_x8.vh" + + wire [17:0] casc_a[0:3]; + wire [15:0] casc_b[0:3]; + + wire ce_a0 = ce_a; + reg ce_a1 = 1'b0; + reg ce_a2 = 1'b0; + + wire ce_b0 = ce_b; + reg ce_b1 = 1'b0; + + always @(posedge clk) begin + ce_a1 <= ce_a0; + ce_a2 <= ce_a1; + ce_b1 <= ce_b0; + end + + + genvar z; + generate for (z=0; z<(NUM_MULTS/2); z=z+1) + // + begin : gen_DSP48E1 + // + modexpng_dsp_slice_wrapper # + ( + .AB_INPUT("DIRECT"), + .B_REG(2) + ) + dsp_direct + ( + .clk (clk), + + .ce_a1 (ce_a0), + .ce_b1 (ce_b0), + .ce_a2 (ce_a1), + .ce_b2 (ce_b1), + .ce_m (ce_m), + .ce_p (ce_p), + .ce_mode (ce_mode), + + .a (a[z*18+:18]), + .b (b), + .p (p[47*2*z+:47]), + + .inmode (5'b00000), + .opmode ({1'b0, mode_z[2*z], 1'b0, 2'b01, 2'b01}), + .alumode (4'b0000), + + .casc_a_in ({18{1'b0}}), + .casc_b_in ({16{1'b0}}), + + .casc_a_out (casc_a[z]), + .casc_b_out (casc_b[z]) + ); + // + modexpng_dsp_slice_wrapper # + ( + .AB_INPUT("CASCADE"), + .B_REG(1) + ) + dsp_cascade + ( + .clk (clk), + + .ce_a1 (ce_a1), + .ce_b1 (1'b0), + .ce_a2 (ce_a2), + .ce_b2 (ce_b1), + .ce_m (ce_m), + .ce_p (ce_p), + .ce_mode (ce_mode), + + .a (a[z*18+:18]), + .b (b), + .p (p[47*(2*z+1)+:47]), + + .inmode (5'b00000), + .opmode ({1'b0, mode_z[2*z+1], 1'b0, 2'b01, 2'b01}), + .alumode (4'b0000), + + .casc_a_in (casc_a[z]), + .casc_b_in (casc_b[z]), + + .casc_a_out (), + .casc_b_out () + ); + // + end + // + endgenerate + + modexpng_dsp_slice_wrapper # + ( + .AB_INPUT("DIRECT"), + .B_REG(2) + ) + dsp_aux + ( + .clk (clk), + + .ce_a1 (ce_a0), + .ce_b1 (ce_b0), + .ce_a2 (ce_a1), + .ce_b2 (ce_b1), + .ce_m (ce_m), + .ce_p (ce_p), + .ce_mode (ce_mode), + + .a (a[4*18+:18]), + .b (b), + .p (p[47*2*4+:47]), + + .inmode (5'b00000), + .opmode ({1'b0, mode_z[2*4], 1'b0, 2'b01, 2'b01}), + .alumode (4'b0000), + + .casc_a_in ({18{1'b0}}), + .casc_b_in ({16{1'b0}}), + + .casc_a_out (), + .casc_b_out () + ); + + +endmodule |