diff options
Diffstat (limited to 'rtl/modexpng_core_top.v')
| -rw-r--r-- | rtl/modexpng_core_top.v | 895 |
1 files changed, 553 insertions, 342 deletions
diff --git a/rtl/modexpng_core_top.v b/rtl/modexpng_core_top.v index e117e5d..6b194dc 100644 --- a/rtl/modexpng_core_top.v +++ b/rtl/modexpng_core_top.v @@ -71,11 +71,13 @@ module modexpng_core_top wire [BANK_ADDR_W -1:0] uop_data_sel_wide_out = uop_data[UOP_W -UOP_OPCODE_W -UOP_CRT_W -UOP_NPQ_W -UOP_AUX_W -UOP_LADDER_W -2*BANK_ADDR_W -1-: BANK_ADDR_W ]; wire [BANK_ADDR_W -1:0] uop_data_sel_narrow_out = uop_data[UOP_W -UOP_OPCODE_W -UOP_CRT_W -UOP_NPQ_W -UOP_AUX_W -UOP_LADDER_W -3*BANK_ADDR_W -1-: BANK_ADDR_W ]; - wire uop_opcode_is_stop = uop_data_opcode == UOP_OPCODE_STOP; - wire uop_opcode_is_io = (uop_data_opcode == UOP_OPCODE_INPUT_TO_WIDE ) || - (uop_data_opcode == UOP_OPCODE_INPUT_TO_NARROW ) || - (uop_data_opcode == UOP_OPCODE_OUTPUT_FROM_NARROW) ; - wire uop_opcode_is_mmm = uop_data_opcode == UOP_OPCODE_MODULAR_MULTIPLY; + wire uop_opcode_is_stop = uop_data_opcode == UOP_OPCODE_STOP ; + wire uop_opcode_is_in = (uop_data_opcode == UOP_OPCODE_INPUT_TO_WIDE ) || + (uop_data_opcode == UOP_OPCODE_INPUT_TO_NARROW ) ; + wire uop_opcode_is_out = uop_data_opcode == UOP_OPCODE_OUTPUT_FROM_NARROW ; + wire uop_opcode_is_mmm = uop_data_opcode == UOP_OPCODE_MODULAR_MULTIPLY ; + wire uop_opcode_is_wrk = (uop_data_opcode == UOP_OPCODE_PROPAGATE_CARRIES ) || + (uop_data_opcode == UOP_OPCODE_COPY_CRT_Y2X ) ; wire [UOP_ADDR_W -1:0] uop_addr_offset = crt_mode ? UOP_ADDR_OFFSET_USING_CRT : UOP_ADDR_OFFSET_WITHOUT_CRT; wire [UOP_ADDR_W -1:0] uop_addr_next = uop_addr + 1'b1; @@ -101,87 +103,135 @@ module modexpng_core_top // // Storage Interfaces (X, Y) // - wire wr_wide_xy_ena_x; - wire [BANK_ADDR_W -1:0] wr_wide_xy_bank_x; - wire [ OP_ADDR_W -1:0] wr_wide_xy_addr_x; - wire [ WORD_EXT_W -1:0] wr_wide_x_din_x; - wire [ WORD_EXT_W -1:0] wr_wide_y_din_x; - - wire wr_narrow_xy_ena_x; - wire [BANK_ADDR_W -1:0] wr_narrow_xy_bank_x; - wire [ OP_ADDR_W -1:0] wr_narrow_xy_addr_x; - wire [ WORD_EXT_W -1:0] wr_narrow_x_din_x; - wire [ WORD_EXT_W -1:0] wr_narrow_y_din_x; - - wire rd_wide_xy_ena_x; - wire rd_wide_xy_ena_aux_x; - wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_x; - wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux_x; - wire [NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr_x; - wire [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux_x; - wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_dout_x; - wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_dout_x; - wire [ WORD_EXT_W -1:0] rd_wide_x_dout_aux_x; - wire [ WORD_EXT_W -1:0] rd_wide_y_dout_aux_x; - - wire rd_narrow_xy_ena_x; - wire [ BANK_ADDR_W -1:0] rd_narrow_xy_bank_x; - wire [ OP_ADDR_W -1:0] rd_narrow_xy_addr_x; - wire [ WORD_EXT_W -1:0] rd_narrow_x_dout_x; - wire [ WORD_EXT_W -1:0] rd_narrow_y_dout_x; - - wire ext_wide_xy_ena_x; - wire [BANK_ADDR_W -1:0] ext_wide_xy_bank_x; - wire [ OP_ADDR_W -1:0] ext_wide_xy_addr_x; - wire [ WORD_EXT_W -1:0] ext_wide_x_din_x; - wire [ WORD_EXT_W -1:0] ext_wide_y_din_x; - - wire ext_narrow_xy_ena_x; - wire [BANK_ADDR_W -1:0] ext_narrow_xy_bank_x; - wire [ OP_ADDR_W -1:0] ext_narrow_xy_addr_x; - wire [ WORD_EXT_W -1:0] ext_narrow_x_din_x; - wire [ WORD_EXT_W -1:0] ext_narrow_y_din_x; - - wire wr_wide_xy_ena_y; - wire [BANK_ADDR_W -1:0] wr_wide_xy_bank_y; - wire [ OP_ADDR_W -1:0] wr_wide_xy_addr_y; - wire [ WORD_EXT_W -1:0] wr_wide_x_din_y; - wire [ WORD_EXT_W -1:0] wr_wide_y_din_y; - - wire wr_narrow_xy_ena_y; - wire [BANK_ADDR_W -1:0] wr_narrow_xy_bank_y; - wire [ OP_ADDR_W -1:0] wr_narrow_xy_addr_y; - wire [ WORD_EXT_W -1:0] wr_narrow_x_din_y; - wire [ WORD_EXT_W -1:0] wr_narrow_y_din_y; - - wire rd_wide_xy_ena_y; - wire rd_wide_xy_ena_aux_y; - wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_y; - wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux_y; - wire [NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr_y; - wire [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux_y; - wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_dout_y; - wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_dout_y; - wire [ WORD_EXT_W -1:0] rd_wide_x_dout_aux_y; - wire [ WORD_EXT_W -1:0] rd_wide_y_dout_aux_y; - - wire rd_narrow_xy_ena_y; - wire [ BANK_ADDR_W -1:0] rd_narrow_xy_bank_y; - wire [ OP_ADDR_W -1:0] rd_narrow_xy_addr_y; - wire [ WORD_EXT_W -1:0] rd_narrow_x_dout_y; - wire [ WORD_EXT_W -1:0] rd_narrow_y_dout_y; - - wire ext_wide_xy_ena_y; - wire [BANK_ADDR_W -1:0] ext_wide_xy_bank_y; - wire [ OP_ADDR_W -1:0] ext_wide_xy_addr_y; - wire [ WORD_EXT_W -1:0] ext_wide_x_din_y; - wire [ WORD_EXT_W -1:0] ext_wide_y_din_y; - - wire ext_narrow_xy_ena_y; - wire [BANK_ADDR_W -1:0] ext_narrow_xy_bank_y; - wire [ OP_ADDR_W -1:0] ext_narrow_xy_addr_y; - wire [ WORD_EXT_W -1:0] ext_narrow_x_din_y; - wire [ WORD_EXT_W -1:0] ext_narrow_y_din_y; + wire wr_wide_xy_ena_x; // \ \ + wire [ BANK_ADDR_W -1:0] wr_wide_xy_bank_x; // | WIDE | WR + wire [ OP_ADDR_W -1:0] wr_wide_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wr_wide_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wr_wide_y_data_x; // / | + // | + wire wr_narrow_xy_ena_x; // \ | + wire [ BANK_ADDR_W -1:0] wr_narrow_xy_bank_x; // | NARROW | + wire [ OP_ADDR_W -1:0] wr_narrow_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wr_narrow_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wr_narrow_y_data_x; // / / + // + wire rd_wide_xy_ena_x; // \ \ + wire rd_wide_xy_ena_aux_x; // | WIDE | RD + wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_x; // | | + wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux_x; // | | + wire [NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr_x; // | | + wire [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux_x; // | | + wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_data_x; // | | + wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_data_x; // | | + wire [ WORD_EXT_W -1:0] rd_wide_x_data_aux_x; // | | + wire [ WORD_EXT_W -1:0] rd_wide_y_data_aux_x; // / | + // | + wire rd_narrow_xy_ena_x; // \ | + wire [ BANK_ADDR_W -1:0] rd_narrow_xy_bank_x; // | NARROW | + wire [ OP_ADDR_W -1:0] rd_narrow_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] rd_narrow_x_data_x; // | | + wire [ WORD_EXT_W -1:0] rd_narrow_y_data_x; // / / + // + wire wrk_rd_wide_xy_ena_x; // \ \ + wire [ BANK_ADDR_W -1:0] wrk_rd_wide_xy_bank_x; // | WIDE | WRK + wire [ OP_ADDR_W -1:0] wrk_rd_wide_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wrk_rd_wide_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wrk_rd_wide_y_data_x; // / | + // | + wire wrk_rd_narrow_xy_ena_x; // \ | + wire [ BANK_ADDR_W -1:0] wrk_rd_narrow_xy_bank_x; // | NARROW | + wire [ OP_ADDR_W -1:0] wrk_rd_narrow_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wrk_rd_narrow_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wrk_rd_narrow_y_data_x; // / / + + wire wrk_wr_wide_xy_ena_x; // \ \ + wire [ BANK_ADDR_W -1:0] wrk_wr_wide_xy_bank_x; // | WIDE | WRK + wire [ OP_ADDR_W -1:0] wrk_wr_wide_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wrk_wr_wide_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wrk_wr_wide_y_data_x; // / | + // | + wire wrk_wr_narrow_xy_ena_x; // \ | + wire [ BANK_ADDR_W -1:0] wrk_wr_narrow_xy_bank_x; // | NARROW | + wire [ OP_ADDR_W -1:0] wrk_wr_narrow_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] wrk_wr_narrow_x_data_x; // | | + wire [ WORD_EXT_W -1:0] wrk_wr_narrow_y_data_x; // / / + // + wire io_wide_xy_ena_x; // \ \ + wire [ BANK_ADDR_W -1:0] io_wide_xy_bank_x; // | WIDE | IO + wire [ OP_ADDR_W -1:0] io_wide_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] io_wide_x_data_x; // | | + wire [ WORD_EXT_W -1:0] io_wide_y_data_x; // / | + // | + wire io_narrow_xy_ena_x; // \ | + wire [ BANK_ADDR_W -1:0] io_narrow_xy_bank_x; // | NARROW | + wire [ OP_ADDR_W -1:0] io_narrow_xy_addr_x; // | | + wire [ WORD_EXT_W -1:0] io_narrow_x_data_x; // | | + wire [ WORD_EXT_W -1:0] io_narrow_y_data_x; // / / + // + wire wr_wide_xy_ena_y; // \ + wire [ BANK_ADDR_W -1:0] wr_wide_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wr_wide_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wr_wide_x_data_y; // + wire [ WORD_EXT_W -1:0] wr_wide_y_data_y; // + // + wire wr_narrow_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] wr_narrow_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wr_narrow_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wr_narrow_x_data_y; // + wire [ WORD_EXT_W -1:0] wr_narrow_y_data_y; // + // + wire rd_wide_xy_ena_y; // + wire rd_wide_xy_ena_aux_y; // + wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_y; // + wire [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux_y; // + wire [NUM_MULTS_HALF * OP_ADDR_W -1:0] rd_wide_xy_addr_y; // + wire [ OP_ADDR_W -1:0] rd_wide_xy_addr_aux_y; // + wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_x_data_y; // + wire [NUM_MULTS_HALF * WORD_EXT_W -1:0] rd_wide_y_data_y; // + wire [ WORD_EXT_W -1:0] rd_wide_x_data_aux_y; // + wire [ WORD_EXT_W -1:0] rd_wide_y_data_aux_y; // + // + wire rd_narrow_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] rd_narrow_xy_bank_y; // + wire [ OP_ADDR_W -1:0] rd_narrow_xy_addr_y; // + wire [ WORD_EXT_W -1:0] rd_narrow_x_data_y; // + wire [ WORD_EXT_W -1:0] rd_narrow_y_data_y; // + // + wire wrk_rd_wide_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] wrk_rd_wide_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wrk_rd_wide_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wrk_rd_wide_x_data_y; // + wire [ WORD_EXT_W -1:0] wrk_rd_wide_y_data_y; // + // + wire wrk_rd_narrow_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] wrk_rd_narrow_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wrk_rd_narrow_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wrk_rd_narrow_x_data_y; // + wire [ WORD_EXT_W -1:0] wrk_rd_narrow_y_data_y; // + + wire wrk_wr_wide_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] wrk_wr_wide_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wrk_wr_wide_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wrk_wr_wide_x_data_y; // + wire [ WORD_EXT_W -1:0] wrk_wr_wide_y_data_y; // + // + wire wrk_wr_narrow_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] wrk_wr_narrow_xy_bank_y; // + wire [ OP_ADDR_W -1:0] wrk_wr_narrow_xy_addr_y; // + wire [ WORD_EXT_W -1:0] wrk_wr_narrow_x_data_y; // + wire [ WORD_EXT_W -1:0] wrk_wr_narrow_y_data_y; // + // + wire io_wide_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] io_wide_xy_bank_y; // + wire [ OP_ADDR_W -1:0] io_wide_xy_addr_y; // + wire [ WORD_EXT_W -1:0] io_wide_x_data_y; // + wire [ WORD_EXT_W -1:0] io_wide_y_data_y; // + // + wire io_narrow_xy_ena_y; // + wire [ BANK_ADDR_W -1:0] io_narrow_xy_bank_y; // + wire [ OP_ADDR_W -1:0] io_narrow_xy_addr_y; // + wire [ WORD_EXT_W -1:0] io_narrow_x_data_y; // + wire [ WORD_EXT_W -1:0] io_narrow_y_data_y; // // @@ -189,38 +239,38 @@ module modexpng_core_top // wire [BANK_ADDR_W -1:0] rcmb_wide_xy_bank_x; wire [ OP_ADDR_W -1:0] rcmb_wide_xy_addr_x; - wire [ WORD_EXT_W -1:0] rcmb_wide_x_dout_x; - wire [ WORD_EXT_W -1:0] rcmb_wide_y_dout_x; + wire [ WORD_EXT_W -1:0] rcmb_wide_x_data_x; + wire [ WORD_EXT_W -1:0] rcmb_wide_y_data_x; wire rcmb_wide_xy_valid_x; wire [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank_x; wire [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr_x; - wire [ WORD_EXT_W -1:0] rcmb_narrow_x_dout_x; - wire [ WORD_EXT_W -1:0] rcmb_narrow_y_dout_x; + wire [ WORD_EXT_W -1:0] rcmb_narrow_x_data_x; + wire [ WORD_EXT_W -1:0] rcmb_narrow_y_data_x; wire rcmb_narrow_xy_valid_x; wire [BANK_ADDR_W -1:0] rcmb_final_xy_bank_x; wire [ OP_ADDR_W -1:0] rcmb_final_xy_addr_x; - wire [ WORD_EXT_W -1:0] rcmb_final_x_dout_x; - wire [ WORD_EXT_W -1:0] rcmb_final_y_dout_x; + wire [ WORD_EXT_W -1:0] rcmb_final_x_data_x; + wire [ WORD_EXT_W -1:0] rcmb_final_y_data_x; wire rcmb_final_xy_valid_x; wire [BANK_ADDR_W -1:0] rcmb_wide_xy_bank_y; wire [ OP_ADDR_W -1:0] rcmb_wide_xy_addr_y; - wire [ WORD_EXT_W -1:0] rcmb_wide_x_dout_y; - wire [ WORD_EXT_W -1:0] rcmb_wide_y_dout_y; + wire [ WORD_EXT_W -1:0] rcmb_wide_x_data_y; + wire [ WORD_EXT_W -1:0] rcmb_wide_y_data_y; wire rcmb_wide_xy_valid_y; wire [BANK_ADDR_W -1:0] rcmb_narrow_xy_bank_y; wire [ OP_ADDR_W -1:0] rcmb_narrow_xy_addr_y; - wire [ WORD_EXT_W -1:0] rcmb_narrow_x_dout_y; - wire [ WORD_EXT_W -1:0] rcmb_narrow_y_dout_y; + wire [ WORD_EXT_W -1:0] rcmb_narrow_x_data_y; + wire [ WORD_EXT_W -1:0] rcmb_narrow_y_data_y; wire rcmb_narrow_xy_valid_y; wire [BANK_ADDR_W -1:0] rcmb_final_xy_bank_y; wire [ OP_ADDR_W -1:0] rcmb_final_xy_addr_y; - wire [ WORD_EXT_W -1:0] rcmb_final_x_dout_y; - wire [ WORD_EXT_W -1:0] rcmb_final_y_dout_y; + wire [ WORD_EXT_W -1:0] rcmb_final_x_data_y; + wire [ WORD_EXT_W -1:0] rcmb_final_y_data_y; wire rcmb_final_xy_valid_y; @@ -229,26 +279,26 @@ module modexpng_core_top // wire [BANK_ADDR_W -1:0] rdct_wide_xy_bank_x; wire [ OP_ADDR_W -1:0] rdct_wide_xy_addr_x; - wire [ WORD_EXT_W -1:0] rdct_wide_x_dout_x; - wire [ WORD_EXT_W -1:0] rdct_wide_y_dout_x; + wire [ WORD_EXT_W -1:0] rdct_wide_x_data_x; + wire [ WORD_EXT_W -1:0] rdct_wide_y_data_x; wire rdct_wide_xy_valid_x; wire [BANK_ADDR_W -1:0] rdct_narrow_xy_bank_x; wire [ OP_ADDR_W -1:0] rdct_narrow_xy_addr_x; - wire [ WORD_EXT_W -1:0] rdct_narrow_x_dout_x; - wire [ WORD_EXT_W -1:0] rdct_narrow_y_dout_x; + wire [ WORD_EXT_W -1:0] rdct_narrow_x_data_x; + wire [ WORD_EXT_W -1:0] rdct_narrow_y_data_x; wire rdct_narrow_xy_valid_x; wire [BANK_ADDR_W -1:0] rdct_wide_xy_bank_y; wire [ OP_ADDR_W -1:0] rdct_wide_xy_addr_y; - wire [ WORD_EXT_W -1:0] rdct_wide_x_dout_y; - wire [ WORD_EXT_W -1:0] rdct_wide_y_dout_y; + wire [ WORD_EXT_W -1:0] rdct_wide_x_data_y; + wire [ WORD_EXT_W -1:0] rdct_wide_y_data_y; wire rdct_wide_xy_valid_y; wire [BANK_ADDR_W -1:0] rdct_narrow_xy_bank_y; wire [ OP_ADDR_W -1:0] rdct_narrow_xy_addr_y; - wire [ WORD_EXT_W -1:0] rdct_narrow_x_dout_y; - wire [ WORD_EXT_W -1:0] rdct_narrow_y_dout_y; + wire [ WORD_EXT_W -1:0] rdct_narrow_x_data_y; + wire [ WORD_EXT_W -1:0] rdct_narrow_y_data_y; wire rdct_narrow_xy_valid_y; @@ -263,14 +313,14 @@ module modexpng_core_top .wr_wide_xy_ena (wr_wide_xy_ena_x), .wr_wide_xy_bank (wr_wide_xy_bank_x), .wr_wide_xy_addr (wr_wide_xy_addr_x), - .wr_wide_x_din (wr_wide_x_din_x), - .wr_wide_y_din (wr_wide_y_din_x), + .wr_wide_x_din (wr_wide_x_data_x), + .wr_wide_y_din (wr_wide_y_data_x), .wr_narrow_xy_ena (wr_narrow_xy_ena_x), .wr_narrow_xy_bank (wr_narrow_xy_bank_x), .wr_narrow_xy_addr (wr_narrow_xy_addr_x), - .wr_narrow_x_din (wr_narrow_x_din_x), - .wr_narrow_y_din (wr_narrow_y_din_x), + .wr_narrow_x_din (wr_narrow_x_data_x), + .wr_narrow_y_din (wr_narrow_y_data_x), .rd_wide_xy_ena (rd_wide_xy_ena_x), .rd_wide_xy_ena_aux (rd_wide_xy_ena_aux_x), @@ -278,16 +328,28 @@ module modexpng_core_top .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_x), .rd_wide_xy_addr (rd_wide_xy_addr_x), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_x), - .rd_wide_x_dout (rd_wide_x_dout_x), - .rd_wide_y_dout (rd_wide_y_dout_x), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_x), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_x), + .rd_wide_x_dout (rd_wide_x_data_x), + .rd_wide_y_dout (rd_wide_y_data_x), + .rd_wide_x_dout_aux (rd_wide_x_data_aux_x), + .rd_wide_y_dout_aux (rd_wide_y_data_aux_x), .rd_narrow_xy_ena (rd_narrow_xy_ena_x), .rd_narrow_xy_bank (rd_narrow_xy_bank_x), .rd_narrow_xy_addr (rd_narrow_xy_addr_x), - .rd_narrow_x_dout (rd_narrow_x_dout_x), - .rd_narrow_y_dout (rd_narrow_y_dout_x) + .rd_narrow_x_dout (rd_narrow_x_data_x), + .rd_narrow_y_dout (rd_narrow_y_data_x), + + .wrk_wide_xy_ena (wrk_rd_wide_xy_ena_x), + .wrk_wide_xy_bank (wrk_rd_wide_xy_bank_x), + .wrk_wide_xy_addr (wrk_rd_wide_xy_addr_x), + .wrk_wide_x_dout (wrk_rd_wide_x_data_x), + .wrk_wide_y_dout (wrk_rd_wide_y_data_x), + + .wrk_narrow_xy_ena (wrk_rd_narrow_xy_ena_x), + .wrk_narrow_xy_bank (wrk_rd_narrow_xy_bank_x), + .wrk_narrow_xy_addr (wrk_rd_narrow_xy_addr_x), + .wrk_narrow_x_dout (wrk_rd_narrow_x_data_x), + .wrk_narrow_y_dout (wrk_rd_narrow_y_data_x) ); modexpng_storage_block storage_block_y @@ -298,14 +360,14 @@ module modexpng_core_top .wr_wide_xy_ena (wr_wide_xy_ena_y), .wr_wide_xy_bank (wr_wide_xy_bank_y), .wr_wide_xy_addr (wr_wide_xy_addr_y), - .wr_wide_x_din (wr_wide_x_din_y), - .wr_wide_y_din (wr_wide_y_din_y), + .wr_wide_x_din (wr_wide_x_data_y), + .wr_wide_y_din (wr_wide_y_data_y), .wr_narrow_xy_ena (wr_narrow_xy_ena_y), .wr_narrow_xy_bank (wr_narrow_xy_bank_y), .wr_narrow_xy_addr (wr_narrow_xy_addr_y), - .wr_narrow_x_din (wr_narrow_x_din_y), - .wr_narrow_y_din (wr_narrow_y_din_y), + .wr_narrow_x_din (wr_narrow_x_data_y), + .wr_narrow_y_din (wr_narrow_y_data_y), .rd_wide_xy_ena (rd_wide_xy_ena_y), .rd_wide_xy_ena_aux (rd_wide_xy_ena_aux_y), @@ -313,16 +375,29 @@ module modexpng_core_top .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_y), .rd_wide_xy_addr (rd_wide_xy_addr_y), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_y), - .rd_wide_x_dout (rd_wide_x_dout_y), - .rd_wide_y_dout (rd_wide_y_dout_y), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_y), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_y), + .rd_wide_x_dout (rd_wide_x_data_y), + .rd_wide_y_dout (rd_wide_y_data_y), + .rd_wide_x_dout_aux (rd_wide_x_data_aux_y), + .rd_wide_y_dout_aux (rd_wide_y_data_aux_y), .rd_narrow_xy_ena (rd_narrow_xy_ena_y), .rd_narrow_xy_bank (rd_narrow_xy_bank_y), .rd_narrow_xy_addr (rd_narrow_xy_addr_y), - .rd_narrow_x_dout (rd_narrow_x_dout_y), - .rd_narrow_y_dout (rd_narrow_y_dout_y) + .rd_narrow_x_dout (rd_narrow_x_data_y), + .rd_narrow_y_dout (rd_narrow_y_data_y), + + .wrk_wide_xy_ena (wrk_rd_wide_xy_ena_y), + .wrk_wide_xy_bank (wrk_rd_wide_xy_bank_y), + .wrk_wide_xy_addr (wrk_rd_wide_xy_addr_y), + .wrk_wide_x_dout (wrk_rd_wide_x_data_y), + .wrk_wide_y_dout (wrk_rd_wide_y_data_y), + + .wrk_narrow_xy_ena (wrk_rd_narrow_xy_ena_y), + .wrk_narrow_xy_bank (wrk_rd_narrow_xy_bank_y), + .wrk_narrow_xy_addr (wrk_rd_narrow_xy_addr_y), + .wrk_narrow_x_dout (wrk_rd_narrow_x_data_y), + .wrk_narrow_y_dout (wrk_rd_narrow_y_data_y) + ); @@ -337,50 +412,62 @@ module modexpng_core_top .wr_wide_xy_ena (wr_wide_xy_ena_x), .wr_wide_xy_bank (wr_wide_xy_bank_x), .wr_wide_xy_addr (wr_wide_xy_addr_x), - .wr_wide_x_din (wr_wide_x_din_x), - .wr_wide_y_din (wr_wide_y_din_x), + .wr_wide_x_dout (wr_wide_x_data_x), + .wr_wide_y_dout (wr_wide_y_data_x), .wr_narrow_xy_ena (wr_narrow_xy_ena_x), .wr_narrow_xy_bank (wr_narrow_xy_bank_x), .wr_narrow_xy_addr (wr_narrow_xy_addr_x), - .wr_narrow_x_din (wr_narrow_x_din_x), - .wr_narrow_y_din (wr_narrow_y_din_x), + .wr_narrow_x_dout (wr_narrow_x_data_x), + .wr_narrow_y_dout (wr_narrow_y_data_x), - .ext_wide_xy_ena (ext_wide_xy_ena_x), - .ext_wide_xy_bank (ext_wide_xy_bank_x), - .ext_wide_xy_addr (ext_wide_xy_addr_x), - .ext_wide_x_din (ext_wide_x_din_x), - .ext_wide_y_din (ext_wide_y_din_x), + .io_wide_xy_ena (io_wide_xy_ena_x), + .io_wide_xy_bank (io_wide_xy_bank_x), + .io_wide_xy_addr (io_wide_xy_addr_x), + .io_wide_x_din (io_wide_x_data_x), + .io_wide_y_din (io_wide_y_data_x), - .ext_narrow_xy_ena (ext_narrow_xy_ena_x), - .ext_narrow_xy_bank (ext_narrow_xy_bank_x), - .ext_narrow_xy_addr (ext_narrow_xy_addr_x), - .ext_narrow_x_din (ext_narrow_x_din_x), - .ext_narrow_y_din (ext_narrow_y_din_x), + .io_narrow_xy_ena (io_narrow_xy_ena_x), + .io_narrow_xy_bank (io_narrow_xy_bank_x), + .io_narrow_xy_addr (io_narrow_xy_addr_x), + .io_narrow_x_din (io_narrow_x_data_x), + .io_narrow_y_din (io_narrow_y_data_x), .rcmb_wide_xy_bank (rcmb_wide_xy_bank_x), .rcmb_wide_xy_addr (rcmb_wide_xy_addr_x), - .rcmb_wide_x_din (rcmb_wide_x_dout_x), - .rcmb_wide_y_din (rcmb_wide_y_dout_x), + .rcmb_wide_x_din (rcmb_wide_x_data_x), + .rcmb_wide_y_din (rcmb_wide_y_data_x), .rcmb_wide_xy_ena (rcmb_wide_xy_valid_x), .rcmb_narrow_xy_bank (rcmb_narrow_xy_bank_x), .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr_x), - .rcmb_narrow_x_din (rcmb_narrow_x_dout_x), - .rcmb_narrow_y_din (rcmb_narrow_y_dout_x), + .rcmb_narrow_x_din (rcmb_narrow_x_data_x), + .rcmb_narrow_y_din (rcmb_narrow_y_data_x), .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid_x), .rdct_wide_xy_bank (rdct_wide_xy_bank_x), .rdct_wide_xy_addr (rdct_wide_xy_addr_x), - .rdct_wide_x_din (rdct_wide_x_dout_x), // TODO: maybe just rename to {x|y}_x, since that's an - .rdct_wide_y_din (rdct_wide_y_dout_x), // internal signal?? + .rdct_wide_x_din (rdct_wide_x_data_x), + .rdct_wide_y_din (rdct_wide_y_data_x), .rdct_wide_xy_valid (rdct_wide_xy_valid_x), .rdct_narrow_xy_bank (rdct_narrow_xy_bank_x), .rdct_narrow_xy_addr (rdct_narrow_xy_addr_x), - .rdct_narrow_x_din (rdct_narrow_x_dout_x), - .rdct_narrow_y_din (rdct_narrow_y_dout_x), - .rdct_narrow_xy_valid (rdct_narrow_xy_valid_x) + .rdct_narrow_x_din (rdct_narrow_x_data_x), + .rdct_narrow_y_din (rdct_narrow_y_data_x), + .rdct_narrow_xy_valid (rdct_narrow_xy_valid_x), + + .wrk_wide_xy_ena (wrk_wr_wide_xy_ena_x), + .wrk_wide_xy_bank (wrk_wr_wide_xy_bank_x), + .wrk_wide_xy_addr (wrk_wr_wide_xy_addr_x), + .wrk_wide_x_din (wrk_wr_wide_x_data_x), + .wrk_wide_y_din (wrk_wr_wide_y_data_x), + + .wrk_narrow_xy_ena (wrk_wr_narrow_xy_ena_x), + .wrk_narrow_xy_bank (wrk_wr_narrow_xy_bank_x), + .wrk_narrow_xy_addr (wrk_wr_narrow_xy_addr_x), + .wrk_narrow_x_din (wrk_wr_narrow_x_data_x), + .wrk_narrow_y_din (wrk_wr_narrow_y_data_x) ); modexpng_storage_manager storage_manager_y @@ -391,51 +478,62 @@ module modexpng_core_top .wr_wide_xy_ena (wr_wide_xy_ena_y), .wr_wide_xy_bank (wr_wide_xy_bank_y), .wr_wide_xy_addr (wr_wide_xy_addr_y), - .wr_wide_x_din (wr_wide_x_din_y), - .wr_wide_y_din (wr_wide_y_din_y), + .wr_wide_x_dout (wr_wide_x_data_y), + .wr_wide_y_dout (wr_wide_y_data_y), .wr_narrow_xy_ena (wr_narrow_xy_ena_y), .wr_narrow_xy_bank (wr_narrow_xy_bank_y), .wr_narrow_xy_addr (wr_narrow_xy_addr_y), - .wr_narrow_x_din (wr_narrow_x_din_y), - .wr_narrow_y_din (wr_narrow_y_din_y), + .wr_narrow_x_dout (wr_narrow_x_data_y), + .wr_narrow_y_dout (wr_narrow_y_data_y), - .ext_wide_xy_ena (ext_wide_xy_ena_y), - .ext_wide_xy_bank (ext_wide_xy_bank_y), - .ext_wide_xy_addr (ext_wide_xy_addr_y), - .ext_wide_x_din (ext_wide_x_din_y), - .ext_wide_y_din (ext_wide_y_din_y), + .io_wide_xy_ena (io_wide_xy_ena_y), + .io_wide_xy_bank (io_wide_xy_bank_y), + .io_wide_xy_addr (io_wide_xy_addr_y), + .io_wide_x_din (io_wide_x_data_y), + .io_wide_y_din (io_wide_y_data_y), - .ext_narrow_xy_ena (ext_narrow_xy_ena_y), - .ext_narrow_xy_bank (ext_narrow_xy_bank_y), - .ext_narrow_xy_addr (ext_narrow_xy_addr_y), - .ext_narrow_x_din (ext_narrow_x_din_y), - .ext_narrow_y_din (ext_narrow_y_din_y), + .io_narrow_xy_ena (io_narrow_xy_ena_y), + .io_narrow_xy_bank (io_narrow_xy_bank_y), + .io_narrow_xy_addr (io_narrow_xy_addr_y), + .io_narrow_x_din (io_narrow_x_data_y), + .io_narrow_y_din (io_narrow_y_data_y), .rcmb_wide_xy_bank (rcmb_wide_xy_bank_y), .rcmb_wide_xy_addr (rcmb_wide_xy_addr_y), - .rcmb_wide_x_din (rcmb_wide_x_dout_y), - .rcmb_wide_y_din (rcmb_wide_y_dout_y), + .rcmb_wide_x_din (rcmb_wide_x_data_y), + .rcmb_wide_y_din (rcmb_wide_y_data_y), .rcmb_wide_xy_ena (rcmb_wide_xy_valid_y), .rcmb_narrow_xy_bank (rcmb_narrow_xy_bank_y), .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr_y), - .rcmb_narrow_x_din (rcmb_narrow_x_dout_y), - .rcmb_narrow_y_din (rcmb_narrow_y_dout_y), + .rcmb_narrow_x_din (rcmb_narrow_x_data_y), + .rcmb_narrow_y_din (rcmb_narrow_y_data_y), .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid_y), .rdct_wide_xy_bank (rdct_wide_xy_bank_y), .rdct_wide_xy_addr (rdct_wide_xy_addr_y), - .rdct_wide_x_din (rdct_wide_x_dout_y), - .rdct_wide_y_din (rdct_wide_y_dout_y), + .rdct_wide_x_din (rdct_wide_x_data_y), + .rdct_wide_y_din (rdct_wide_y_data_y), .rdct_wide_xy_valid (rdct_wide_xy_valid_y), .rdct_narrow_xy_bank (rdct_narrow_xy_bank_y), .rdct_narrow_xy_addr (rdct_narrow_xy_addr_y), - .rdct_narrow_x_din (rdct_narrow_x_dout_y), - .rdct_narrow_y_din (rdct_narrow_y_dout_y), - .rdct_narrow_xy_valid (rdct_narrow_xy_valid_y) - + .rdct_narrow_x_din (rdct_narrow_x_data_y), + .rdct_narrow_y_din (rdct_narrow_y_data_y), + .rdct_narrow_xy_valid (rdct_narrow_xy_valid_y), + + .wrk_wide_xy_ena (wrk_wr_wide_xy_ena_y), + .wrk_wide_xy_bank (wrk_wr_wide_xy_bank_y), + .wrk_wide_xy_addr (wrk_wr_wide_xy_addr_y), + .wrk_wide_x_din (wrk_wr_wide_x_data_y), + .wrk_wide_y_din (wrk_wr_wide_y_data_y), + + .wrk_narrow_xy_ena (wrk_wr_narrow_xy_ena_y), + .wrk_narrow_xy_bank (wrk_wr_narrow_xy_bank_y), + .wrk_narrow_xy_addr (wrk_wr_narrow_xy_addr_y), + .wrk_narrow_x_din (wrk_wr_narrow_x_data_y), + .wrk_narrow_y_din (wrk_wr_narrow_y_data_y) ); @@ -444,16 +542,16 @@ module modexpng_core_top // wire io_in_1_en; wire [BANK_ADDR_W + OP_ADDR_W -1:0] io_in_1_addr; - wire [ WORD_W -1:0] io_in_1_dout; + wire [ WORD_W -1:0] io_in_1_data; wire io_in_2_en; wire [BANK_ADDR_W + OP_ADDR_W -1:0] io_in_2_addr; - wire [ WORD_W -1:0] io_in_2_dout; + wire [ WORD_W -1:0] io_in_2_data; wire io_out_en; wire io_out_we; wire [BANK_ADDR_W + OP_ADDR_W -1:0] io_out_addr; - wire [ WORD_W -1:0] io_out_din; + wire [ WORD_W -1:0] io_out_data; // TODO: Separate reset for clock domains (core/bus)??? @@ -472,16 +570,16 @@ module modexpng_core_top .in_1_en (io_in_1_en), .in_1_addr (io_in_1_addr), - .in_1_dout (io_in_1_dout), + .in_1_dout (io_in_1_data), .in_2_en (io_in_2_en), .in_2_addr (io_in_2_addr), - .in_2_dout (io_in_2_dout), + .in_2_dout (io_in_2_data), .out_en (io_out_en), .out_we (io_out_we), .out_addr (io_out_addr), - .out_din (io_out_din) + .out_din (io_out_data) ); @@ -497,59 +595,65 @@ module modexpng_core_top reg [OP_ADDR_W -1:0] io_mgr_word_index_last; reg [UOP_OPCODE_W -1:0] io_mgr_opcode; + wire [WORD_W -1:0] wrk_rd_narrow_x_data_x_trunc = wrk_rd_narrow_x_data_x[WORD_W-1:0]; + wire [WORD_W -1:0] wrk_rd_narrow_x_data_y_trunc = wrk_rd_narrow_x_data_y[WORD_W-1:0]; + modexpng_io_manager io_manager ( - .clk (clk), - .rst (rst), + .clk (clk), + .rst (rst), - .ena (io_mgr_ena), - .rdy (io_mgr_rdy), + .ena (io_mgr_ena), + .rdy (io_mgr_rdy), - .sel_crt (io_mgr_sel_crt), - .sel_aux (io_mgr_sel_aux), - .sel_in (io_mgr_sel_in), - .sel_out (io_mgr_sel_out), + .sel_crt (io_mgr_sel_crt), + .sel_aux (io_mgr_sel_aux), + .sel_in (io_mgr_sel_in), + .sel_out (io_mgr_sel_out), - .opcode (io_mgr_opcode), + .opcode (io_mgr_opcode), - .word_index_last (io_mgr_word_index_last), + .word_index_last (io_mgr_word_index_last), - .ext_wide_xy_ena_x (ext_wide_xy_ena_x), - .ext_wide_xy_bank_x (ext_wide_xy_bank_x), - .ext_wide_xy_addr_x (ext_wide_xy_addr_x), - .ext_wide_x_din_x (ext_wide_x_din_x), - .ext_wide_y_din_x (ext_wide_y_din_x), - - .ext_narrow_xy_ena_x (ext_narrow_xy_ena_x), - .ext_narrow_xy_bank_x (ext_narrow_xy_bank_x), - .ext_narrow_xy_addr_x (ext_narrow_xy_addr_x), - .ext_narrow_x_din_x (ext_narrow_x_din_x), - .ext_narrow_y_din_x (ext_narrow_y_din_x), - - .ext_wide_xy_ena_y (ext_wide_xy_ena_y), - .ext_wide_xy_bank_y (ext_wide_xy_bank_y), - .ext_wide_xy_addr_y (ext_wide_xy_addr_y), - .ext_wide_x_din_y (ext_wide_x_din_y), - .ext_wide_y_din_y (ext_wide_y_din_y), - - .ext_narrow_xy_ena_y (ext_narrow_xy_ena_y), - .ext_narrow_xy_bank_y (ext_narrow_xy_bank_y), - .ext_narrow_xy_addr_y (ext_narrow_xy_addr_y), - .ext_narrow_x_din_y (ext_narrow_x_din_y), - .ext_narrow_y_din_y (ext_narrow_y_din_y), + .io_wide_xy_ena_x (io_wide_xy_ena_x), + .io_wide_xy_bank_x (io_wide_xy_bank_x), + .io_wide_xy_addr_x (io_wide_xy_addr_x), + .io_wide_x_din_x (io_wide_x_data_x), + .io_wide_y_din_x (io_wide_y_data_x), + + .io_narrow_xy_ena_x (io_narrow_xy_ena_x), + .io_narrow_xy_bank_x (io_narrow_xy_bank_x), + .io_narrow_xy_addr_x (io_narrow_xy_addr_x), + .io_narrow_x_din_x (io_narrow_x_data_x), + .io_narrow_y_din_x (io_narrow_y_data_x), + + .io_wide_xy_ena_y (io_wide_xy_ena_y), + .io_wide_xy_bank_y (io_wide_xy_bank_y), + .io_wide_xy_addr_y (io_wide_xy_addr_y), + .io_wide_x_din_y (io_wide_x_data_y), + .io_wide_y_din_y (io_wide_y_data_y), + + .io_narrow_xy_ena_y (io_narrow_xy_ena_y), + .io_narrow_xy_bank_y (io_narrow_xy_bank_y), + .io_narrow_xy_addr_y (io_narrow_xy_addr_y), + .io_narrow_x_din_y (io_narrow_x_data_y), + .io_narrow_y_din_y (io_narrow_y_data_y), - .io_in_1_en (io_in_1_en), - .io_in_1_addr (io_in_1_addr), - .io_in_1_dout (io_in_1_dout), + .io_in_1_en (io_in_1_en), + .io_in_1_addr (io_in_1_addr), + .io_in_1_din (io_in_1_data), - .io_in_2_en (io_in_2_en), - .io_in_2_addr (io_in_2_addr), - .io_in_2_dout (io_in_2_dout), + .io_in_2_en (io_in_2_en), + .io_in_2_addr (io_in_2_addr), + .io_in_2_din (io_in_2_data), - .io_out_en (io_out_en), - .io_out_we (io_out_we), - .io_out_addr (io_out_addr), - .io_out_din (io_out_din) + .io_out_en (io_out_en), + .io_out_we (io_out_we), + .io_out_addr (io_out_addr), + .io_out_dout (io_out_data), + + .wrk_narrow_x_din_x_trunc (wrk_rd_narrow_x_data_x_trunc), + .wrk_narrow_x_din_y_trunc (wrk_rd_narrow_x_data_y_trunc) ); @@ -608,33 +712,33 @@ module modexpng_core_top .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_x), .rd_wide_xy_addr (rd_wide_xy_addr_x), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_x), - .rd_wide_x_dout (rd_wide_x_dout_x), - .rd_wide_y_dout (rd_wide_y_dout_x), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_x), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_x), + .rd_wide_x_din (rd_wide_x_data_x), + .rd_wide_y_din (rd_wide_y_data_x), + .rd_wide_x_din_aux (rd_wide_x_data_aux_x), + .rd_wide_y_din_aux (rd_wide_y_data_aux_x), .rd_narrow_xy_ena (rd_narrow_xy_ena_x), .rd_narrow_xy_bank (rd_narrow_xy_bank_x), .rd_narrow_xy_addr (rd_narrow_xy_addr_x), - .rd_narrow_x_dout (rd_narrow_x_dout_x), - .rd_narrow_y_dout (rd_narrow_y_dout_x), + .rd_narrow_x_din (rd_narrow_x_data_x), + .rd_narrow_y_din (rd_narrow_y_data_x), .rcmb_wide_xy_bank (rcmb_wide_xy_bank_x), .rcmb_wide_xy_addr (rcmb_wide_xy_addr_x), - .rcmb_wide_x_dout (rcmb_wide_x_dout_x), - .rcmb_wide_y_dout (rcmb_wide_y_dout_x), + .rcmb_wide_x_dout (rcmb_wide_x_data_x), + .rcmb_wide_y_dout (rcmb_wide_y_data_x), .rcmb_wide_xy_valid (rcmb_wide_xy_valid_x), .rcmb_narrow_xy_bank (rcmb_narrow_xy_bank_x), .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr_x), - .rcmb_narrow_x_dout (rcmb_narrow_x_dout_x), - .rcmb_narrow_y_dout (rcmb_narrow_y_dout_x), + .rcmb_narrow_x_dout (rcmb_narrow_x_data_x), + .rcmb_narrow_y_dout (rcmb_narrow_y_data_x), .rcmb_narrow_xy_valid (rcmb_narrow_xy_valid_x), .rcmb_xy_bank (rcmb_final_xy_bank_x), .rcmb_xy_addr (rcmb_final_xy_addr_x), - .rcmb_x_dout (rcmb_final_x_dout_x), - .rcmb_y_dout (rcmb_final_y_dout_x), + .rcmb_x_dout (rcmb_final_x_data_x), + .rcmb_y_dout (rcmb_final_y_data_x), .rcmb_xy_valid (rcmb_final_xy_valid_x), .rdct_ena (rdct_ena_x), @@ -663,33 +767,33 @@ module modexpng_core_top .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_y), .rd_wide_xy_addr (rd_wide_xy_addr_y), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_y), - .rd_wide_x_dout (rd_wide_x_dout_y), - .rd_wide_y_dout (rd_wide_y_dout_y), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_y), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_y), + .rd_wide_x_din (rd_wide_x_data_y), + .rd_wide_y_din (rd_wide_y_data_y), + .rd_wide_x_din_aux (rd_wide_x_data_aux_y), + .rd_wide_y_din_aux (rd_wide_y_data_aux_y), .rd_narrow_xy_ena (rd_narrow_xy_ena_y), .rd_narrow_xy_bank (rd_narrow_xy_bank_y), .rd_narrow_xy_addr (rd_narrow_xy_addr_y), - .rd_narrow_x_dout (rd_narrow_x_dout_y), - .rd_narrow_y_dout (rd_narrow_y_dout_y), + .rd_narrow_x_din (rd_narrow_x_data_y), + .rd_narrow_y_din (rd_narrow_y_data_y), .rcmb_wide_xy_bank (rcmb_wide_xy_bank_y), .rcmb_wide_xy_addr (rcmb_wide_xy_addr_y), - .rcmb_wide_x_dout (rcmb_wide_x_dout_y), - .rcmb_wide_y_dout (rcmb_wide_y_dout_y), + .rcmb_wide_x_dout (rcmb_wide_x_data_y), + .rcmb_wide_y_dout (rcmb_wide_y_data_y), .rcmb_wide_xy_valid (rcmb_wide_xy_valid_y), .rcmb_narrow_xy_bank (rcmb_narrow_xy_bank_y), .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr_y), - .rcmb_narrow_x_dout (rcmb_narrow_x_dout_y), - .rcmb_narrow_y_dout (rcmb_narrow_y_dout_y), + .rcmb_narrow_x_dout (rcmb_narrow_x_data_y), + .rcmb_narrow_y_dout (rcmb_narrow_y_data_y), .rcmb_narrow_xy_valid (rcmb_narrow_xy_valid_y), .rcmb_xy_bank (rcmb_final_xy_bank_y), .rcmb_xy_addr (rcmb_final_xy_addr_y), - .rcmb_x_dout (rcmb_final_x_dout_y), - .rcmb_y_dout (rcmb_final_y_dout_y), + .rcmb_x_dout (rcmb_final_x_data_y), + .rcmb_y_dout (rcmb_final_y_data_y), .rcmb_xy_valid (rcmb_final_xy_valid_y), .rdct_ena (rdct_ena_y), @@ -723,25 +827,25 @@ module modexpng_core_top .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_x), .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_x), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_x), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_x), + .rd_wide_x_din_aux (rd_wide_x_data_aux_x), + .rd_wide_y_din_aux (rd_wide_y_data_aux_x), .rcmb_final_xy_bank (rcmb_final_xy_bank_x), .rcmb_final_xy_addr (rcmb_final_xy_addr_x), - .rcmb_final_x_dout (rcmb_final_x_dout_x), - .rcmb_final_y_dout (rcmb_final_y_dout_x), + .rcmb_final_x_din (rcmb_final_x_data_x), + .rcmb_final_y_din (rcmb_final_y_data_x), .rcmb_final_xy_valid (rcmb_final_xy_valid_x), .rdct_wide_xy_bank (rdct_wide_xy_bank_x), .rdct_wide_xy_addr (rdct_wide_xy_addr_x), - .rdct_wide_x_dout (rdct_wide_x_dout_x), - .rdct_wide_y_dout (rdct_wide_y_dout_x), + .rdct_wide_x_dout (rdct_wide_x_data_x), + .rdct_wide_y_dout (rdct_wide_y_data_x), .rdct_wide_xy_valid (rdct_wide_xy_valid_x), .rdct_narrow_xy_bank (rdct_narrow_xy_bank_x), .rdct_narrow_xy_addr (rdct_narrow_xy_addr_x), - .rdct_narrow_x_dout (rdct_narrow_x_dout_x), - .rdct_narrow_y_dout (rdct_narrow_y_dout_x), + .rdct_narrow_x_dout (rdct_narrow_x_data_x), + .rdct_narrow_y_dout (rdct_narrow_y_data_x), .rdct_narrow_xy_valid (rdct_narrow_xy_valid_x) ); @@ -760,30 +864,110 @@ module modexpng_core_top .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux_y), .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux_y), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux_y), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux_y), + .rd_wide_x_din_aux (rd_wide_x_data_aux_y), + .rd_wide_y_din_aux (rd_wide_y_data_aux_y), .rcmb_final_xy_bank (rcmb_final_xy_bank_y), .rcmb_final_xy_addr (rcmb_final_xy_addr_y), - .rcmb_final_x_dout (rcmb_final_x_dout_y), - .rcmb_final_y_dout (rcmb_final_y_dout_y), + .rcmb_final_x_din (rcmb_final_x_data_y), + .rcmb_final_y_din (rcmb_final_y_data_y), .rcmb_final_xy_valid (rcmb_final_xy_valid_y), .rdct_wide_xy_bank (rdct_wide_xy_bank_y), .rdct_wide_xy_addr (rdct_wide_xy_addr_y), - .rdct_wide_x_dout (rdct_wide_x_dout_y), - .rdct_wide_y_dout (rdct_wide_y_dout_y), + .rdct_wide_x_dout (rdct_wide_x_data_y), + .rdct_wide_y_dout (rdct_wide_y_data_y), .rdct_wide_xy_valid (rdct_wide_xy_valid_y), .rdct_narrow_xy_bank (rdct_narrow_xy_bank_y), .rdct_narrow_xy_addr (rdct_narrow_xy_addr_y), - .rdct_narrow_x_dout (rdct_narrow_x_dout_y), - .rdct_narrow_y_dout (rdct_narrow_y_dout_y), + .rdct_narrow_x_dout (rdct_narrow_x_data_y), + .rdct_narrow_y_dout (rdct_narrow_y_data_y), .rdct_narrow_xy_valid (rdct_narrow_xy_valid_y) ); // + // General Worker + // + reg wrk_ena = 1'b0; + wire wrk_rdy; + + reg [ BANK_ADDR_W -1:0] wrk_sel_wide_in; + reg [ BANK_ADDR_W -1:0] wrk_sel_wide_out; + reg [ BANK_ADDR_W -1:0] wrk_sel_narrow_in; + reg [ BANK_ADDR_W -1:0] wrk_sel_narrow_out; + reg [ OP_ADDR_W -1:0] wrk_word_index_last; + reg [UOP_OPCODE_W -1:0] wrk_opcode; + + modexpng_general_worker general_worker + ( + .clk (clk), + .rst (rst), + + .ena (wrk_ena), + .rdy (wrk_rdy), + + .sel_narrow_in (wrk_sel_narrow_in), + .sel_narrow_out (wrk_sel_narrow_out), + .sel_wide_in (wrk_sel_wide_in), + .sel_wide_out (wrk_sel_wide_out), + + .opcode (wrk_opcode), + + .word_index_last (wrk_word_index_last), + + .wrk_rd_wide_xy_ena_x (wrk_rd_wide_xy_ena_x), + .wrk_rd_wide_xy_bank_x (wrk_rd_wide_xy_bank_x), + .wrk_rd_wide_xy_addr_x (wrk_rd_wide_xy_addr_x), + .wrk_rd_wide_x_din_x (wrk_rd_wide_x_data_x), + .wrk_rd_wide_y_din_x (wrk_rd_wide_y_data_x), + + .wrk_rd_narrow_xy_ena_x (wrk_rd_narrow_xy_ena_x), + .wrk_rd_narrow_xy_bank_x (wrk_rd_narrow_xy_bank_x), + .wrk_rd_narrow_xy_addr_x (wrk_rd_narrow_xy_addr_x), + .wrk_rd_narrow_x_din_x (wrk_rd_narrow_x_data_x), + .wrk_rd_narrow_y_din_x (wrk_rd_narrow_y_data_x), + + .wrk_rd_wide_xy_ena_y (wrk_rd_wide_xy_ena_y), + .wrk_rd_wide_xy_bank_y (wrk_rd_wide_xy_bank_y), + .wrk_rd_wide_xy_addr_y (wrk_rd_wide_xy_addr_y), + .wrk_rd_wide_x_din_y (wrk_rd_wide_x_data_y), + .wrk_rd_wide_y_din_y (wrk_rd_wide_y_data_y), + + .wrk_rd_narrow_xy_ena_y (wrk_rd_narrow_xy_ena_y), + .wrk_rd_narrow_xy_bank_y (wrk_rd_narrow_xy_bank_y), + .wrk_rd_narrow_xy_addr_y (wrk_rd_narrow_xy_addr_y), + .wrk_rd_narrow_x_din_y (wrk_rd_narrow_x_data_y), + .wrk_rd_narrow_y_din_y (wrk_rd_narrow_y_data_y), + + .wrk_wr_wide_xy_ena_x (wrk_wr_wide_xy_ena_x), + .wrk_wr_wide_xy_bank_x (wrk_wr_wide_xy_bank_x), + .wrk_wr_wide_xy_addr_x (wrk_wr_wide_xy_addr_x), + .wrk_wr_wide_x_dout_x (wrk_wr_wide_x_data_x), + .wrk_wr_wide_y_dout_x (wrk_wr_wide_y_data_x), + + .wrk_wr_narrow_xy_ena_x (wrk_wr_narrow_xy_ena_x), + .wrk_wr_narrow_xy_bank_x (wrk_wr_narrow_xy_bank_x), + .wrk_wr_narrow_xy_addr_x (wrk_wr_narrow_xy_addr_x), + .wrk_wr_narrow_x_dout_x (wrk_wr_narrow_x_data_x), + .wrk_wr_narrow_y_dout_x (wrk_wr_narrow_y_data_x), + + .wrk_wr_wide_xy_ena_y (wrk_wr_wide_xy_ena_y), + .wrk_wr_wide_xy_bank_y (wrk_wr_wide_xy_bank_y), + .wrk_wr_wide_xy_addr_y (wrk_wr_wide_xy_addr_y), + .wrk_wr_wide_x_dout_y (wrk_wr_wide_x_data_y), + .wrk_wr_wide_y_dout_y (wrk_wr_wide_y_data_y), + + .wrk_wr_narrow_xy_ena_y (wrk_wr_narrow_xy_ena_y), + .wrk_wr_narrow_xy_bank_y (wrk_wr_narrow_xy_bank_y), + .wrk_wr_narrow_xy_addr_y (wrk_wr_narrow_xy_addr_y), + .wrk_wr_narrow_x_dout_y (wrk_wr_narrow_x_data_y), + .wrk_wr_narrow_y_dout_y (wrk_wr_narrow_y_data_y) + ); + + + // // uOP Completion Detector // reg uop_exit_from_busy; @@ -792,10 +976,10 @@ module modexpng_core_top // uop_exit_from_busy = 0; // - if (uop_opcode_is_io) uop_exit_from_busy = ~io_mgr_ena & io_mgr_rdy; - if (uop_opcode_is_mmm) uop_exit_from_busy = ~mmm_ena & mmm_rdy; - //if (uop_data_opcode_is_add) uop_exit_from_busy = ~mod_add_ena & mod_add_rdy; - //if (uop_data_opcode_is_sub) uop_exit_from_busy = ~mod_sub_ena & mod_sub_rdy; + if (uop_opcode_is_in) uop_exit_from_busy = ~io_mgr_ena & io_mgr_rdy; + if (uop_opcode_is_out) uop_exit_from_busy = (~io_mgr_ena & io_mgr_rdy) & (~mmm_ena & mmm_rdy); + if (uop_opcode_is_mmm) uop_exit_from_busy = ~mmm_ena & mmm_rdy ; + if (uop_opcode_is_wrk) uop_exit_from_busy = ~wrk_ena & wrk_rdy ; // end @@ -809,10 +993,12 @@ module modexpng_core_top io_mgr_ena <= 1'b0; mmm_ena_x <= 1'b0; mmm_ena_y <= 1'b0; + wrk_ena <= 1'b0; end else begin - io_mgr_ena <= uop_fsm_state == UOP_FSM_STATE_DECODE ? uop_opcode_is_io : 1'b0; - mmm_ena_x <= uop_fsm_state == UOP_FSM_STATE_DECODE ? uop_opcode_is_mmm : 1'b0; - mmm_ena_y <= uop_fsm_state == UOP_FSM_STATE_DECODE ? uop_opcode_is_mmm : 1'b0; + io_mgr_ena <= uop_fsm_state == UOP_FSM_STATE_DECODE ? (uop_opcode_is_in || uop_opcode_is_out) : 1'b0; + mmm_ena_x <= uop_fsm_state == UOP_FSM_STATE_DECODE ? uop_opcode_is_mmm : 1'b0; + mmm_ena_y <= uop_fsm_state == UOP_FSM_STATE_DECODE ? uop_opcode_is_mmm : 1'b0; + wrk_ena <= uop_fsm_state == UOP_FSM_STATE_DECODE ? (uop_opcode_is_wrk || uop_opcode_is_out) : 1'b0; end // @@ -825,6 +1011,7 @@ module modexpng_core_top if (uop_fsm_state == UOP_FSM_STATE_DECODE) begin // io_mgr_opcode <= uop_data_opcode; + wrk_opcode <= uop_data_opcode; // case (uop_data_opcode) // @@ -842,6 +1029,15 @@ module modexpng_core_top io_mgr_sel_out <= uop_data_sel_narrow_out; end // + UOP_OPCODE_OUTPUT_FROM_NARROW: begin + io_mgr_sel_crt <= uop_data_crt; + io_mgr_sel_aux <= UOP_AUX_DNC; + io_mgr_sel_in <= BANK_DNC; + io_mgr_sel_out <= uop_data_sel_narrow_out; + // + wrk_sel_narrow_in <= uop_data_sel_narrow_in; + end + // UOP_OPCODE_MODULAR_MULTIPLY: begin // case (uop_data_ladder) @@ -856,10 +1052,21 @@ module modexpng_core_top {mmm_sel_narrow_in_x, mmm_sel_narrow_in_y } <= {2{uop_data_sel_narrow_in }}; {rdct_sel_wide_out_x, rdct_sel_wide_out_y } <= {2{uop_data_sel_wide_out }}; {rdct_sel_narrow_out_x, rdct_sel_narrow_out_y} <= {2{uop_data_sel_narrow_out }}; - // end // + UOP_OPCODE_PROPAGATE_CARRIES: begin + wrk_sel_narrow_in <= uop_data_sel_narrow_in; + wrk_sel_narrow_out <= uop_data_sel_narrow_out; + end + // + UOP_OPCODE_COPY_CRT_Y2X: begin + wrk_sel_wide_in <= uop_data_sel_wide_in; + wrk_sel_wide_out <= uop_data_sel_wide_out; + wrk_sel_narrow_in <= uop_data_sel_narrow_in; + wrk_sel_narrow_out <= uop_data_sel_narrow_out; + end + // endcase // end @@ -887,6 +1094,9 @@ module modexpng_core_top {rdct_word_index_last_x, rdct_word_index_last_y } <= {2{uop_npq_is_n ? word_index_last_n : word_index_last_pq }}; end // + UOP_OPCODE_PROPAGATE_CARRIES: + wrk_word_index_last = uop_npq_is_n ? word_index_last_n : word_index_last_pq; + // endcase // end @@ -945,87 +1155,88 @@ module modexpng_core_top // // X.X // - $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); - $write("X.X.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[0*256+i]); $write("\n"); - $write("X.X.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[1*256+i]); $write("\n"); - $write("X.X.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[2*256+i]); $write("\n"); - $write("X.X.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[3*256+i]); $write("\n"); - $write("X.X.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[4*256+i]); $write("\n"); - $write("X.X.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[5*256+i]); $write("\n"); - $write("X.X.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[6*256+i]); $write("\n"); - $write("X.X.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_x.mem[7*256+i]); $write("\n"); - $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); - $write("X.X.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[0*256+i]); $write("\n"); - $write("X.X.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[1*256+i]); $write("\n"); - $write("X.X.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[2*256+i]); $write("\n"); - $write("X.X.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[3*256+i]); $write("\n"); - $write("X.X.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[4*256+i]); $write("\n"); - $write("X.X.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[5*256+i]); $write("\n"); - $write("X.X.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[6*256+i]); $write("\n"); - $write("X.X.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_x.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); + $write("X.X.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[0*256+i]); $write("\n"); + $write("X.X.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[1*256+i]); $write("\n"); + $write("X.X.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[2*256+i]); $write("\n"); + $write("X.X.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[3*256+i]); $write("\n"); + $write("X.X.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[4*256+i]); $write("\n"); + $write("X.X.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[5*256+i]); $write("\n"); + $write("X.X.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[6*256+i]); $write("\n"); + $write("X.X.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_x.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); + $write("X.X.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[0*256+i]); $write("\n"); + $write("X.X.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[1*256+i]); $write("\n"); + $write("X.X.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[2*256+i]); $write("\n"); + $write("X.X.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[3*256+i]); $write("\n"); + $write("X.X.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[4*256+i]); $write("\n"); + $write("X.X.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[5*256+i]); $write("\n"); + $write("X.X.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[6*256+i]); $write("\n"); + $write("X.X.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_x.mem[7*256+i]); $write("\n"); // // X.Y // - $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); - $write("X.Y.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[0*256+i]); $write("\n"); - $write("X.Y.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[1*256+i]); $write("\n"); - $write("X.Y.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[2*256+i]); $write("\n"); - $write("X.Y.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[3*256+i]); $write("\n"); - $write("X.Y.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[4*256+i]); $write("\n"); - $write("X.Y.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[5*256+i]); $write("\n"); - $write("X.Y.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[6*256+i]); $write("\n"); - $write("X.Y.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_bram_y.mem[7*256+i]); $write("\n"); - $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); - $write("X.Y.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[0*256+i]); $write("\n"); - $write("X.Y.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[1*256+i]); $write("\n"); - $write("X.Y.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[2*256+i]); $write("\n"); - $write("X.Y.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[3*256+i]); $write("\n"); - $write("X.Y.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[4*256+i]); $write("\n"); - $write("X.Y.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[5*256+i]); $write("\n"); - $write("X.Y.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[6*256+i]); $write("\n"); - $write("X.Y.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide_bram[0].wide_bram_y.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); + $write("X.Y.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[0*256+i]); $write("\n"); + $write("X.Y.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[1*256+i]); $write("\n"); + $write("X.Y.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[2*256+i]); $write("\n"); + $write("X.Y.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[3*256+i]); $write("\n"); + $write("X.Y.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[4*256+i]); $write("\n"); + $write("X.Y.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[5*256+i]); $write("\n"); + $write("X.Y.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[6*256+i]); $write("\n"); + $write("X.Y.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.narrow_y.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); + $write("X.Y.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[0*256+i]); $write("\n"); + $write("X.Y.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[1*256+i]); $write("\n"); + $write("X.Y.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[2*256+i]); $write("\n"); + $write("X.Y.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[3*256+i]); $write("\n"); + $write("X.Y.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[4*256+i]); $write("\n"); + $write("X.Y.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[5*256+i]); $write("\n"); + $write("X.Y.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[6*256+i]); $write("\n"); + $write("X.Y.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_x.gen_wide[0].wide_y.mem[7*256+i]); $write("\n"); // // Y.X // - $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); - $write("Y.X.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[0*256+i]); $write("\n"); - $write("Y.X.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[1*256+i]); $write("\n"); - $write("Y.X.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[2*256+i]); $write("\n"); - $write("Y.X.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[3*256+i]); $write("\n"); - $write("Y.X.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[4*256+i]); $write("\n"); - $write("Y.X.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[5*256+i]); $write("\n"); - $write("Y.X.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[6*256+i]); $write("\n"); - $write("Y.X.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_x.mem[7*256+i]); $write("\n"); - $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); - $write("Y.X.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[0*256+i]); $write("\n"); - $write("Y.X.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[1*256+i]); $write("\n"); - $write("Y.X.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[2*256+i]); $write("\n"); - $write("Y.X.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[3*256+i]); $write("\n"); - $write("Y.X.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[4*256+i]); $write("\n"); - $write("Y.X.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[5*256+i]); $write("\n"); - $write("Y.X.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[6*256+i]); $write("\n"); - $write("Y.X.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_x.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); + $write("Y.X.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[0*256+i]); $write("\n"); + $write("Y.X.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[1*256+i]); $write("\n"); + $write("Y.X.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[2*256+i]); $write("\n"); + $write("Y.X.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[3*256+i]); $write("\n"); + $write("Y.X.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[4*256+i]); $write("\n"); + $write("Y.X.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[5*256+i]); $write("\n"); + $write("Y.X.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[6*256+i]); $write("\n"); + $write("Y.X.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_x.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); + $write("Y.X.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[0*256+i]); $write("\n"); + $write("Y.X.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[1*256+i]); $write("\n"); + $write("Y.X.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[2*256+i]); $write("\n"); + $write("Y.X.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[3*256+i]); $write("\n"); + $write("Y.X.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[4*256+i]); $write("\n"); + $write("Y.X.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[5*256+i]); $write("\n"); + $write("Y.X.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[6*256+i]); $write("\n"); + $write("Y.X.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_x.mem[7*256+i]); $write("\n"); // // Y.Y // - $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); - $write("Y.Y.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[0*256+i]); $write("\n"); - $write("Y.Y.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[1*256+i]); $write("\n"); - $write("Y.Y.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[2*256+i]); $write("\n"); - $write("Y.Y.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[3*256+i]); $write("\n"); - $write("Y.Y.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[4*256+i]); $write("\n"); - $write("Y.Y.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[5*256+i]); $write("\n"); - $write("Y.Y.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[6*256+i]); $write("\n"); - $write("Y.Y.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_bram_y.mem[7*256+i]); $write("\n"); - $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); - $write("Y.Y.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[0*256+i]); $write("\n"); - $write("Y.Y.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[1*256+i]); $write("\n"); - $write("Y.Y.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[2*256+i]); $write("\n"); - $write("Y.Y.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[3*256+i]); $write("\n"); - $write("Y.Y.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[4*256+i]); $write("\n"); - $write("Y.Y.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[5*256+i]); $write("\n"); - $write("Y.Y.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[6*256+i]); $write("\n"); - $write("Y.Y.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide_bram[0].wide_bram_y.mem[7*256+i]); $write("\n"); // + $write(" "); for (i=0; i<64; i=i+1) $write("[ %3d ] ", i); $write("\n"); + $write("Y.Y.NARROW.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[0*256+i]); $write("\n"); + $write("Y.Y.NARROW.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[1*256+i]); $write("\n"); + $write("Y.Y.NARROW.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[2*256+i]); $write("\n"); + $write("Y.Y.NARROW.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[3*256+i]); $write("\n"); + $write("Y.Y.NARROW.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[4*256+i]); $write("\n"); + $write("Y.Y.NARROW.COEFF: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[5*256+i]); $write("\n"); + $write("Y.Y.NARROW.Q: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[6*256+i]); $write("\n"); + $write("Y.Y.NARROW.EXT: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.narrow_y.mem[7*256+i]); $write("\n"); + $write(" "); for (i=0; i<64; i=i+1) $write(" ------ "); $write("\n"); + $write("Y.Y.WIDE.A: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[0*256+i]); $write("\n"); + $write("Y.Y.WIDE.B: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[1*256+i]); $write("\n"); + $write("Y.Y.WIDE.C: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[2*256+i]); $write("\n"); + $write("Y.Y.WIDE.D: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[3*256+i]); $write("\n"); + $write("Y.Y.WIDE.E: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[4*256+i]); $write("\n"); + $write("Y.Y.WIDE.N: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[5*256+i]); $write("\n"); + $write("Y.Y.WIDE.L: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[6*256+i]); $write("\n"); + $write("Y.Y.WIDE.H: "); for (i=0; i<64; i=i+1) $write("0x%05x ", storage_block_y.gen_wide[0].wide_y.mem[7*256+i]); $write("\n"); + // end // |