diff options
Diffstat (limited to 'bench/tb_mmm_dual_x8.v')
| -rw-r--r-- | bench/tb_mmm_dual_x8.v | 102 |
1 files changed, 68 insertions, 34 deletions
diff --git a/bench/tb_mmm_dual_x8.v b/bench/tb_mmm_dual_x8.v index 7e54d09..1188f92 100644 --- a/bench/tb_mmm_dual_x8.v +++ b/bench/tb_mmm_dual_x8.v @@ -7,7 +7,6 @@ module tb_mmm_dual_x8; // Headers // `include "../rtl/modexpng_parameters.vh" - //`include "../rtl_1/modexpng_mmm_fsm_old.vh" // @@ -352,7 +351,7 @@ module tb_mmm_dual_x8; modexpng_mmm_dual uut ( .clk (clk), - .rst (rst), + .rst_n (~rst), .ena (ena), .rdy (rdy), @@ -362,6 +361,7 @@ module tb_mmm_dual_x8; .word_index_last_minus1 (word_index_last_minus1), .force_unity_b (1'b0), .only_reduce (1'b0), + .just_multiply (1'b0), .sel_wide_in (BANK_WIDE_A), .sel_narrow_in (BANK_NARROW_A), @@ -372,16 +372,16 @@ module tb_mmm_dual_x8; .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux), .rd_wide_xy_addr (rd_wide_xy_addr), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux), - .rd_wide_x_dout (rd_wide_x_dout), - .rd_wide_y_dout (rd_wide_y_dout), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux), + .rd_wide_x_din (rd_wide_x_dout), + .rd_wide_y_din (rd_wide_y_dout), + .rd_wide_x_din_aux (rd_wide_x_dout_aux), + .rd_wide_y_din_aux (rd_wide_y_dout_aux), .rd_narrow_xy_ena (rd_narrow_xy_ena), .rd_narrow_xy_bank (rd_narrow_xy_bank), .rd_narrow_xy_addr (rd_narrow_xy_addr), - .rd_narrow_x_dout (rd_narrow_x_dout), - .rd_narrow_y_dout (rd_narrow_y_dout), + .rd_narrow_x_din (rd_narrow_x_dout), + .rd_narrow_y_din (rd_narrow_y_dout), .rcmb_wide_xy_bank (rcmb_wide_xy_bank), .rcmb_wide_xy_addr (rcmb_wide_xy_addr), @@ -412,7 +412,7 @@ module tb_mmm_dual_x8; modexpng_reductor reductor ( .clk (clk), - .rst (rst), + .rst_n (~rst), .ena (rdct_ena), .rdy (rdct_rdy), @@ -422,15 +422,13 @@ module tb_mmm_dual_x8; .sel_wide_out (BANK_WIDE_B), .sel_narrow_out (BANK_NARROW_B), - .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux), - .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux), + .rd_wide_x_din_aux (rd_wide_x_dout_aux), + .rd_wide_y_din_aux (rd_wide_y_dout_aux), .rcmb_final_xy_bank (rcmb_final_xy_bank), .rcmb_final_xy_addr (rcmb_final_xy_addr), - .rcmb_final_x_dout (rcmb_final_x_dout), - .rcmb_final_y_dout (rcmb_final_y_dout), + .rcmb_final_x_din (rcmb_final_x_dout), + .rcmb_final_y_din (rcmb_final_y_dout), .rcmb_final_xy_valid (rcmb_final_xy_valid), .rdct_wide_xy_bank (rdct_wide_xy_bank), @@ -452,7 +450,7 @@ module tb_mmm_dual_x8; modexpng_storage_block storage_block ( .clk (clk), - .rst (rst), + .rst_n (~rst), .wr_wide_xy_ena (wr_wide_xy_ena), .wr_wide_xy_bank (wr_wide_xy_bank), @@ -481,37 +479,49 @@ module tb_mmm_dual_x8; .rd_narrow_xy_bank (rd_narrow_xy_bank), .rd_narrow_xy_addr (rd_narrow_xy_addr), .rd_narrow_x_dout (rd_narrow_x_dout), - .rd_narrow_y_dout (rd_narrow_y_dout) + .rd_narrow_y_dout (rd_narrow_y_dout), + + .wrk_wide_xy_ena (1'b0), + .wrk_wide_xy_bank (), + .wrk_wide_xy_addr (), + .wrk_wide_x_dout (), + .wrk_wide_y_dout (), + + .wrk_narrow_xy_ena (1'b0), + .wrk_narrow_xy_bank (), + .wrk_narrow_xy_addr (), + .wrk_narrow_x_dout (), + .wrk_narrow_y_dout () ); modexpng_storage_manager storage_manager ( .clk (clk), - .rst (rst), + .rst_n (~rst), .wr_wide_xy_ena (wr_wide_xy_ena), .wr_wide_xy_bank (wr_wide_xy_bank), .wr_wide_xy_addr (wr_wide_xy_addr), - .wr_wide_x_din (wr_wide_x_din), - .wr_wide_y_din (wr_wide_y_din), + .wr_wide_x_dout (wr_wide_x_din), + .wr_wide_y_dout (wr_wide_y_din), .wr_narrow_xy_ena (wr_narrow_xy_ena), .wr_narrow_xy_bank (wr_narrow_xy_bank), .wr_narrow_xy_addr (wr_narrow_xy_addr), - .wr_narrow_x_din (wr_narrow_x_din), - .wr_narrow_y_din (wr_narrow_y_din), + .wr_narrow_x_dout (wr_narrow_x_din), + .wr_narrow_y_dout (wr_narrow_y_din), - .ext_wide_xy_ena (ext_wide_xy_ena), - .ext_wide_xy_bank (ext_wide_xy_bank), - .ext_wide_xy_addr (ext_wide_xy_addr), - .ext_wide_x_din (ext_wide_x_din), - .ext_wide_y_din (ext_wide_y_din), - - .ext_narrow_xy_ena (ext_narrow_xy_ena), - .ext_narrow_xy_bank (ext_narrow_xy_bank), - .ext_narrow_xy_addr (ext_narrow_xy_addr), - .ext_narrow_x_din (ext_narrow_x_din), - .ext_narrow_y_din (ext_narrow_y_din), + .io_wide_xy_ena (ext_wide_xy_ena), + .io_wide_xy_bank (ext_wide_xy_bank), + .io_wide_xy_addr (ext_wide_xy_addr), + .io_wide_x_din (ext_wide_x_din), + .io_wide_y_din (ext_wide_y_din), + + .io_narrow_xy_ena (ext_narrow_xy_ena), + .io_narrow_xy_bank (ext_narrow_xy_bank), + .io_narrow_xy_addr (ext_narrow_xy_addr), + .io_narrow_x_din (ext_narrow_x_din), + .io_narrow_y_din (ext_narrow_y_din), .rcmb_wide_xy_bank (rcmb_wide_xy_bank), .rcmb_wide_xy_addr (rcmb_wide_xy_addr), @@ -523,7 +533,31 @@ module tb_mmm_dual_x8; .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr), .rcmb_narrow_x_din (rcmb_narrow_x_dout), .rcmb_narrow_y_din (rcmb_narrow_y_dout), - .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid) + .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid), + + .rdct_wide_xy_bank (), + .rdct_wide_xy_addr (), + .rdct_wide_x_din (), + .rdct_wide_y_din (), + .rdct_wide_xy_valid (1'b0), + + .rdct_narrow_xy_bank (), + .rdct_narrow_xy_addr (), + .rdct_narrow_x_din (), + .rdct_narrow_y_din (), + .rdct_narrow_xy_valid (1'b0), + + .wrk_wide_xy_ena (1'b0), + .wrk_wide_xy_bank (), + .wrk_wide_xy_addr (), + .wrk_wide_x_din (), + .wrk_wide_y_din (), + + .wrk_narrow_xy_ena (1'b0), + .wrk_narrow_xy_bank (), + .wrk_narrow_xy_addr (), + .wrk_narrow_x_din (), + .wrk_narrow_y_din () ); |