Further work:

 - added core wrapper
 - fixed module resets across entire core (all the resets are now consistently
   active-low)
 - continued refactoring

1 files changed, 4 insertions, 4 deletions

diff --git a/rtl/modexpng_storage_block.v b/rtl/modexpng_storage_block.v
index 5a03b24..4b81e0b 100644
--- a/rtl/modexpng_storage_block.v
+++ b/rtl/modexpng_storage_block.v
@@ -1,6 +1,6 @@
 module modexpng_storage_block
 (
-    clk, rst,
+    clk, rst_n,
     
     wr_wide_xy_ena,
     wr_wide_xy_bank,
@@ -55,7 +55,7 @@ module modexpng_storage_block
     // Ports
     //
     input                                         clk;
-    input                                         rst;
+    input                                         rst_n;
 
     input                                         wr_wide_xy_ena;
     input  [                  BANK_ADDR_W   -1:0] wr_wide_xy_bank;
@@ -108,9 +108,9 @@ module modexpng_storage_block
     reg wrk_wide_xy_reg_ena    = 1'b0;
     reg wrk_narrow_xy_reg_ena  = 1'b0;
 
-    always @(posedge clk)
+    always @(posedge clk or negedge rst_n)
         //
-        if (rst) begin
+        if (!rst_n) begin
             rd_wide_xy_reg_ena     <= 1'b0;
             rd_wide_xy_reg_ena_aux <= 1'b0;
             rd_narrow_xy_reg_ena   <= 1'b0;