diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 13:04:07 +0300 |
| commit | 72902f5b40ac695786f5103d2a5a456c6c7ee83f (patch) | |
| tree | 59a644e74fa4fdc25c92b8d261150ef4899323f5 /rtl/modexpng_io_block.v | |
| parent | 9eac252242c69e51a38a9a88c87b564dd40b6257 (diff) | |
Redesigned the testbench. Core clock does not necessarily need to be twice
faster than the bus clock now. It can be the same, or say four times faster.
Diffstat (limited to 'rtl/modexpng_io_block.v')
| -rw-r--r-- | rtl/modexpng_io_block.v | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/rtl/modexpng_io_block.v b/rtl/modexpng_io_block.v index 06ce2b1..6d008aa 100644 --- a/rtl/modexpng_io_block.v +++ b/rtl/modexpng_io_block.v @@ -82,12 +82,12 @@ module modexpng_io_block wire [ BUS_DATA_W -1:0] bus_data_rd_input_1; wire [ BUS_DATA_W -1:0] bus_data_rd_output; - wire bus_we_input_1 = bus_we && (bus_addr_msb == 2'd0); - wire bus_we_input_2 = bus_we && (bus_addr_msb == 2'd1); + wire bus_we_input_1 = bus_we && (bus_addr_msb == 2'd1); + wire bus_we_input_2 = bus_we && (bus_addr_msb == 2'd2); - wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'b00); - wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'b01); - wire bus_cs_output = bus_cs && (bus_addr_msb == 2'b10); + wire bus_cs_input_1 = bus_cs && (bus_addr_msb == 2'd1); + wire bus_cs_input_2 = bus_cs && (bus_addr_msb == 2'd2); + wire bus_cs_output = bus_cs && (bus_addr_msb == 2'd3); /* INPUT_1 */ `MODEXPNG_TDP_36K_X16_X32 bram_input_1 @@ -125,7 +125,6 @@ module modexpng_io_block .doutb (in_2_dout) // ); - /* OUTPUT */ `MODEXPNG_SDP_36K_X32_X16 bram_output ( @@ -152,10 +151,10 @@ module modexpng_io_block // case (bus_addr_msb_dly) // - 2'd0: bus_data_rd_mux = bus_data_rd_input_1; - 2'd1: bus_data_rd_mux = 32'hDEADC0DE; - 2'd2: bus_data_rd_mux = bus_data_rd_output; - 2'd3: bus_data_rd_mux = 32'hDEADC0DE; + 2'd0: bus_data_rd_mux = 32'hDEADC0DE; + 2'd1: bus_data_rd_mux = bus_data_rd_input_1; + 2'd2: bus_data_rd_mux = 32'hDEADC0DE; + 2'd3: bus_data_rd_mux = bus_data_rd_output; // endcase |