Started working on the pipelined Montgomery modular multiplier. Currently can

do the "square" part of the multiplication, i.e. compute the twice larger
intermediate product AB = A * B.

2 files changed, 236 insertions, 0 deletions

diff --git a/rtl/dsp/dsp_array.v b/rtl/dsp/dsp_array.v
new file mode 100644
index 0000000..178f87f
--- /dev/null
+++ b/rtl/dsp/dsp_array.v
@@ -0,0 +1,111 @@
+module dsp_array
+(
+    input             clk,
+    
+    input             ce_a,
+    input             ce_b,
+    input             ce_m,
+    input             ce_p,
+    input             ce_mode,
+
+    input  [8   -1:0] mode_z,
+    
+    input  [4*18-1:0] a,
+    input  [1*17-1:0] b,
+    output [8*47-1:0] p
+);
+
+    `include "../modexpng_parameters_x8.vh"
+    
+    wire [17:0] casc_a[0:3];
+    wire [16:0] casc_b[0:3];
+    
+    wire ce_a0 = ce_a;
+    reg  ce_a1 = 1'b0;
+    reg  ce_a2 = 1'b0;
+    
+    wire ce_b0 = ce_b;
+    reg  ce_b1 = 1'b0;
+    
+    always @(posedge clk) begin
+        ce_a1 <= ce_a0;
+        ce_a2 <= ce_a1;
+        ce_b1 <= ce_b0;
+    end
+        
+    
+    genvar z;
+    generate for (z=0; z<(NUM_MULTS/2); z=z+1)
+        //
+        begin : DSP48E1
+            //        
+            dsp_slice #
+            (
+                .AB_INPUT("DIRECT"),
+                .B_REG(2)
+            )
+            dsp_direct
+            (
+                .clk            (clk),
+                
+                .ce_a1          (ce_a0),
+                .ce_b1          (ce_b0),
+                .ce_a2          (ce_a1),
+                .ce_b2          (ce_b1),
+                .ce_m           (ce_m),
+                .ce_p           (ce_p),
+                .ce_mode        (ce_mode),
+                
+                .a              (a[z*18+:18]),
+                .b              (b),
+                .p              (p[47*2*z+:47]),
+                
+                .inmode         (5'b00000),
+                .opmode         ({1'b0, mode_z[2*z], 1'b0, 2'b01, 2'b01}),
+                .alumode        (4'b0000),
+                
+                .casc_a_in      ({17{1'b0}}),
+                .casc_b_in      ({17{1'b0}}),
+                
+                .casc_a_out     (casc_a[z]),
+                .casc_b_out     (casc_b[z])
+            );
+            //
+            dsp_slice #
+            (
+                .AB_INPUT("CASCADE"),
+                .B_REG(1)
+            )
+            dsp_cascade
+            (
+                .clk            (clk),
+                
+                .ce_a1          (ce_a1),
+                .ce_b1          (1'b0),
+                .ce_a2          (ce_a2),
+                .ce_b2          (ce_b1),
+                .ce_m           (ce_m),
+                .ce_p           (ce_p),
+                .ce_mode        (ce_mode),
+                
+                .a              (a[z*18+:18]),
+                .b              (b),
+                .p              (p[47*(2*z+1)+:47]),
+                
+                .inmode         (5'b00000),
+                .opmode         ({1'b0, mode_z[2*z+1], 1'b0, 2'b01, 2'b01}),
+                .alumode        (4'b0000),
+                
+                .casc_a_in      (casc_a[z]),
+                .casc_b_in      (casc_b[z]),
+                
+                .casc_a_out     (),
+                .casc_b_out     ()
+            );
+            //            
+        end
+        //
+    endgenerate
+
+
+endmodule
diff --git a/rtl/dsp/dsp_slice.v b/rtl/dsp/dsp_slice.v
new file mode 100644
index 0000000..9f1298b
--- /dev/null
+++ b/rtl/dsp/dsp_slice.v
@@ -0,0 +1,125 @@
+module dsp_slice #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    input         clk,
+    input         ce_a1,
+    input         ce_b1,
+    input         ce_a2,
+    input         ce_b2,
+    input         ce_m,
+    input         ce_p,
+    input         ce_mode,
+    input  [17:0] a,
+    input  [16:0] b,
+    output [46:0] p,
+    input  [ 4:0] inmode,
+    input  [ 6:0] opmode,
+    input  [ 3:0] alumode,
+    input  [17:0] casc_a_in,
+    input  [16:0] casc_b_in,
+    output [17:0] casc_a_out,
+    output [16:0] casc_b_out
+);
+
+    wire [30-18-1:0] casc_a_dummy;
+    wire [18-17-1:0] casc_b_dummy;
+    wire [48-47-1:0] p_dummy;
+    
+    DSP48E1 #
+    (
+        .AREG                   (2),
+        .BREG                   (B_REG),
+        .CREG                   (0),
+        .DREG                   (0),
+        .ADREG                  (0),
+        .MREG                   (1),
+        .PREG                   (1),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
+        .INMODEREG              (0),
+        .OPMODEREG              (1),
+        .ALUMODEREG             (0),
+        .CARRYINREG             (0),
+        .CARRYINSELREG          (0),
+
+        .A_INPUT                (AB_INPUT),
+        .B_INPUT                (AB_INPUT),
+
+        .USE_DPORT              ("FALSE"),
+        .USE_MULT               ("DYNAMIC"),
+        .USE_SIMD               ("ONE48"),
+
+        .MASK                   (48'h3fffffffffff),
+        .PATTERN                (48'h000000000000),
+        .SEL_MASK               ("MASK"),
+        .SEL_PATTERN            ("PATTERN"),
+        
+        .USE_PATTERN_DETECT     ("NO_PATDET"),
+        .AUTORESET_PATDET       ("NO_RESET")
+    )
+    DSP48E1_inst
+    (
+        .CLK                (clk),
+    
+        .CEA1               (ce_a1),
+        .CEB1               (ce_b1),
+        .CEA2               (ce_a2),
+        .CEB2               (ce_b2),
+        .CEAD               (1'b0),
+        .CEC                (1'b0),
+        .CED                (1'b0),
+        .CEM                (ce_m),
+        .CEP                (ce_p),
+        .CEINMODE           (1'b0),
+        .CECTRL             (ce_mode),
+        .CEALUMODE          (1'b0),
+        .CECARRYIN          (1'b0),
+
+        .A                  ({{(30-18){1'b0}}, a}),
+        .B                  ({{(18-17){1'b0}}, b}),
+        .C                  ({48{1'b0}}),
+        .D                  ({25{1'b0}}),
+        .P                  ({p_dummy, p}),
+        
+        .INMODE             (inmode),
+        .OPMODE             (opmode),
+        .ALUMODE            (alumode),
+
+        .ACIN               ({{(30-18){1'b0}}, casc_a_in}),
+        .BCIN               ({{(18-17){1'b0}}, casc_b_in}),
+        .ACOUT              ({casc_a_dummy, casc_a_out}),
+        .BCOUT              ({casc_b_dummy, casc_b_out}),
+        .PCIN               ({48{1'b0}}),
+        .PCOUT              (),
+        .CARRYCASCIN        (1'b0),
+        .CARRYCASCOUT       (),
+ 
+        .RSTA               (1'b0),
+        .RSTB               (1'b0),
+        .RSTC               (1'b0),
+        .RSTD               (1'b0),
+        .RSTM               (1'b0),
+        .RSTP               (1'b0),
+        .RSTINMODE          (1'b0),
+        .RSTCTRL            (1'b0),
+        .RSTALUMODE         (1'b0),
+        .RSTALLCARRYIN      (1'b0),
+
+        .UNDERFLOW          (),
+        .OVERFLOW           (),
+        .PATTERNDETECT      (),
+        .PATTERNBDETECT     (),
+
+        .CARRYIN            (1'b0),
+        .CARRYOUT           (),
+        .CARRYINSEL         (3'b000),
+
+        .MULTSIGNIN         (1'b0),
+        .MULTSIGNOUT        ()
+ );
+
+
+endmodule