diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 15:19:30 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 15:19:30 +0300 |
| commit | edd5efd83266bb534d7cde3d908e74749278ed96 (patch) | |
| tree | c7b5295fc73f1904d9206630ca1eee897ba05cdc /bench/tb_wrapper.v | |
| parent | 584393ac5fc9bbe80887702ec2fc97bee999c5e7 (diff) | |
Reworked testbench, clk_sys and clk_core can now have any ratio, not
necessarily 1:2.
Fixed compile-time issue where ISE fails to place two DSP slices next to each
other, if A and/or B cascade path(s) between then are partially connected.
Basically, if cascade is used, entire bus must be connected.
Diffstat (limited to 'bench/tb_wrapper.v')
| -rw-r--r-- | bench/tb_wrapper.v | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/bench/tb_wrapper.v b/bench/tb_wrapper.v index 2000ec5..0c51228 100644 --- a/bench/tb_wrapper.v +++ b/bench/tb_wrapper.v @@ -58,7 +58,7 @@ module tb_wrapper; .clk (clk_bus), .rst_n (rst_n), - .clk_core (clk), + .clk_core (clk_bus), .cs (bus_cs), .we (bus_we), @@ -83,10 +83,11 @@ module tb_wrapper; begin sync_clk_bus; - wait_clk_bus_ticks(10); + wait_clk_bus_ticks(100); rst_n = 1'b1; - wait_clk_bus_ticks(10); + wait_clk_bus_ticks(100); + /* bus_read('h11, to); $display("modulus_bits = %0d", to); ti = 100; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 510; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); @@ -103,8 +104,8 @@ module tb_wrapper; ti = 1026; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 4094; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); - ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); - ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); + ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);*/ + ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);/* ti = 4097; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 4098; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); @@ -135,11 +136,17 @@ module tb_wrapper; ti = 1026; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); ti = 4094; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); + ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);*/ + ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);/* ti = 4097; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); ti = 4098; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - + */ + //ti = 0; bus_write('h08, ti); + //ti = 2; bus_write('h08, ti); + //ti = 0; bus_write('h08, ti); + //ti = 2; bus_write('h08, ti); + //ti = 0; bus_write('h08, ti); + //ti = 2; bus_write('h08, ti); end endtask |