path: root/rtl/modexpng_sdp_36k_x18_wrapper_xilinx.v

//======================================================================
//
// Copyright: 2019, The Commons Conservancy Cryptech Project
// SPDX-License-Identifier: BSD-3-Clause
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the copyright holder nor the names of its
//   contributors may be used to endorse or promote products derived from
//   this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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//
//======================================================================

module modexpng_sdp_36k_x18_wrapper_xilinx
(
    clk,
    
    ena, wea,
    addra, dina,
    
    enb, regceb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                 clk;
    
    input                                 ena;
    input                                 wea;
    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addra;
    input  [             WORD_EXT_W -1:0] dina;
    
    input                                 enb;
    input                                 regceb;
    input  [BANK_ADDR_W + OP_ADDR_W -1:0] addrb;
    output [             WORD_EXT_W -1:0] doutb;

    //
    // BRAM_SDP_MACRO
    //
    BRAM_SDP_MACRO #
    (
        .DEVICE                 ("7SERIES"),
        
        .BRAM_SIZE              ("36Kb"),
        
        .WRITE_WIDTH            (WORD_EXT_W),
        .READ_WIDTH             (WORD_EXT_W),
        
        .DO_REG                 (1),
        .WRITE_MODE             ("READ_FIRST"),
        
        .SRVAL                  (72'h000000000000000000),
        .INIT                   (72'h000000000000000000),

        .INIT_FILE              ("NONE"),
        .SIM_COLLISION_CHECK    ("NONE")
    )
    BRAM_SDP_MACRO_inst
    (
        .RST        (1'b0),
    
        .WRCLK      (clk),
        .WREN       (ena),
        .WE         ({2{wea}}),
        .WRADDR     (addra),
        .DI         (dina),
        
        .RDCLK      (clk),
        .RDEN       (enb),
        .REGCE      (regceb),
        .RDADDR     (addrb),
        .DO         (doutb)
    );
    
endmodule