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2017-07-19Added pre-multiplication step.Pavel V. Shatov (Meister)
2017-07-19Finished modular exponentiation module:Pavel V. Shatov (Meister)
2017-07-18Started adding exponentiator module w/ testbench.Pavel V. Shatov (Meister)
2017-07-13Systolic multiplier simplified a bit:Pavel V. Shatov (Meister)
2017-07-10 * made separate file for low-level settingsPavel V. Shatov (Meister)
2017-07-04Fixed generic/vendor low-level primitives switch.Pavel V. Shatov (Meister)
2017-07-04Fixing generic/vendor primitive switching...Pavel V. Shatov (Meister)
2017-07-01Started porting generic multiplier to Xilinx primitives.Pavel V. Shatov (Meister)
2017-07-01Added generic/vendor-specific primitive selector for simulation.Pavel V. Shatov (Meister)
2017-07-01Cleaned up Verilog sourcesPavel V. Shatov (Meister)
2017-07-01Added 512-bit test vectorPavel V. Shatov (Meister)
2017-07-01Finished modulus-dependent coefficient calculation module:Pavel V. Shatov (Meister)
2017-06-27Added test vectors, use scripts from the C model to (re-)generate them.Pavel V. Shatov (Meister)
2017-06-27Added Montgomery modulus-dependent coefficient calculation blockPavel V. Shatov (Meister)
2017-06-27Added Montgomery factor calculation blockPavel V. Shatov (Meister)
2017-06-27Added systolic modular multiplier w/ testbench.Pavel V. Shatov (Meister)
2017-06-27Added generic processing elements.Pavel V. Shatov (Meister)
2017-06-27Start conversion to systolic architecture.Pavel V. Shatov (Meister)
2016-06-14Initial commitPaul Selkirk