core/math/modexpa7 - Modular exponentiation using the Artix-7 FPGA

Branch	Commit message	Author	Age
master	Use primitives from core/lib	Pavel V. Shatov (Meister)	6 years

Tag	Download	Author	Age
v0.20	commit 06dadb7faa...	Pavel V. Shatov (Meister)	8 years

Age	Commit message	Author
2017-08-07	* Added readme filev0.20	Pavel V. Shatov (Meister)
2017-08-06	Added demo program that shows how to talk to the core and sign something.	Pavel V. Shatov (Meister)
2017-08-06	* Moved systolic processing element array into a separate module.	Pavel V. Shatov (Meister)
2017-07-27	Work in progress.	Pavel V. Shatov (Meister)
2017-07-25	Work in progress.	Pavel V. Shatov (Meister)
2017-07-25	Wide operand loader needs simplification...	Pavel V. Shatov (Meister)
2017-07-25	Trying to fix the bug during calculation of SN in systolic multiplier.	Pavel V. Shatov (Meister)
2017-07-24	Started adding top-level wrapper.	Pavel V. Shatov (Meister)
2017-07-23	Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes ...	Pavel V. Shatov (Meister)
2017-07-23	Converted pe_t array into a FIFO too. No more nasty messages during synthesis...	Pavel V. Shatov (Meister)
[...]

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